ATmega256RZAV Atmel Corporation, ATmega256RZAV Datasheet - Page 29

• Manufacturer Part Number: ATmega256RZAV
• Manufacturer: Atmel Corporation

Specifications of ATmega256RZAV

• Flash (kbytes): 256 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

9.1.1
9.1.2
2549N–AVR–05/11
Using the External Memory Interface
Address Latch Requirements
The interface consists of:
•
•
•
•
The control bits for the External Memory Interface are located in two registers, the External
Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 9-3 on page 31
high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the
XMEM interface is enabled, also an internal access will cause activity on address, data and ALE
ports, but the RD and WR strobes will not toggle during internal access. When the External
Memory Interface is disabled, the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM.
SRAM to the AVR using an octal latch (typically “74 × 573” or equivalent) which is transparent
when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
•
•
•
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
11
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
through
AD7:0: Multiplexed low-order address bus and data bus
ALE: Address latch enable
RD: Read strobe
WR: Write strobe
D to Q propagation delay (t
Data setup time before G low (t
Data (address) hold time after G low (
• A15:8: High-order address bus (configurable number of bits)
Tables 31-18
h
= 5ns. Refer to t
(this figure shows the wave forms without wait-states). When ALE goes from
on pages
SU
PD
ATmega640/1280/1281/2560/2561
) must not exceed address valid to ALE low (t
)
LAXX_LD
379
SU
Figure 9-2 on page 30
)
- 382. The D-to-Q propagation delay (t
/t
TH
LLAXX_ST
)
in
“External Data Memory Timing” Tables 31-
illustrates how to connect an external
“I/O-Ports” on page
PD
AVLLC
) must be taken
70. The XMEM
) minus PCB
Fig-
29