ATmega256RZAV Atmel Corporation, ATmega256RZAV Datasheet - Page 17

• Manufacturer Part Number: ATmega256RZAV
• Manufacturer: Atmel Corporation

Specifications of ATmega256RZAV

• Flash (kbytes): 256 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

7.6.1
7.6.2
7.7
2549N–AVR–05/11
Instruction Execution Timing
RAMPZ – Extended Z-pointer Register for ELPM/SPM
EIND – Extended Indirect Register
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in
Figure 7-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation
of EIND, ZH, and ZL, as shown in
EIND setting.
Figure 7-5.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-6 on page 18
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (
Individually)
Bit (Z-pointer)
Bit
0x3C (0x5C)
Read/Write
Initial Value
Bit (Individual-
ly)
Bit
pointer)
Figure 7-4.
(Indirect-
RAMPZ7
Note that LPM is not affected by the RAMPZ setting.
EIND7
The Z-pointer used by ELPM and SPM
The Indirect-pointer used by EICALL and EIJMP
R/W
R/W
7
0
7
0
23
23
7
7
RAMPZ6
EIND6
shows the parallel instruction fetches and instruction executions enabled
R/W
R/W
EIND
RAMPZ
6
0
6
0
RAMPZ5
EIND5
R/W
R/W
ATmega640/1280/1281/2560/2561
16
5
0
5
0
0
16
0
Figure 7-5.
CPU
, directly generated from the selected clock source for the
RAMPZ4
EIND4
R/W
R/W
4
0
4
0
15
7
15
7
Note that ICALL and IJMP are not affected by the
RAMPZ3
EIND3
R/W
R/W
ZH
3
0
3
0
ZH
RAMPZ2
EIND2
R/W
R/W
2
0
2
0
0
8
0
8
RAMPZ1
EIND1
R/W
R/W
1
0
1
0
7
7
7
7
RAMPZ0
EIND0
R/W
R/W
ZL
0
0
0
0
ZL
RAMPZ
EIND
0
0
0
0
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