ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 210

• Manufacturer Part Number: ATmega88
• Manufacturer: Atmel Corporation

Specifications of ATmega88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.2.2
22.3
22.3.1
22.3.2
2545T–AVR–05/11
Data transfer and frame format
Electrical interconnection
Transferring bits
START and STOP conditions
Table 22-1.
The PRTWI bit in
the 2-wire serial interface.
As depicted in
age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the operation of the
interface. A low level on a TWI bus line is generated when one or more TWI devices output a
zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resis-
tors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical charac-
teristics of the TWI is given in
sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one
valid for bus speeds up to 400kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 22-2. Data validity.
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
Term
Slave
Transmitter
Receiver
SDA
SCL
TWI terminology.
Figure 22-1 on page
Description
The device addressed by a master.
The device placing data on the bus.
The device reading data from the bus.
“Minimizing power consumption” on page 41
“2-wire serial interface characteristics” on page
Data stable
209, both bus lines are connected to the positive supply volt-
Data change
Data stable
ATmega48/88/168
must be written to zero to enable
308. Two different
210