ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 69

• Manufacturer Part Number: ATmega88
• Manufacturer: Atmel Corporation

Specifications of ATmega88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.2.4
13.2.5
2545T–AVR–05/11
PCICR – Pin change interrupt control register
PCIFR – Pin change interrupt flag register
• Bit 7..3 - Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 2 - PCIE2: Pin change interrupt enable 2
When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-
rupt. The corresponding interrupt of pin change interrupt request is executed from the PCI2
interrupt vector. PCINT23..16 pins are enabled individually by the PCMSK2 register.
• Bit 1 - PCIE1: Pin change interrupt enable 1
When the PCIE1 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an inter-
rupt. The corresponding interrupt of pin change interrupt request is executed from the PCI1
interrupt vector. PCINT14..8 pins are enabled individually by the PCMSK1 register.
• Bit 0 - PCIE0: Pin change interrupt enable 0
When the PCIE0 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt
vector. PCINT7..0 pins are enabled individually by the PCMSK0 register.
• Bit 7..3 - Res: Reserved bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 2 - PCIF2: Pin change interrupt flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 - PCIF1: Pin change interrupt flag 1
When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit
(0x68)
Read/write
Initial value
Bit
0x1B (0x3B)
Read/write
Initial value
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
PCIE2
PCIF2
ATmega48/88/168
R/W
R/W
2
0
2
0
PCIE1
PCIF1
R/W
R/W
1
0
1
0
PCIE0
PCIF0
R/W
R/W
0
0
0
0
PCICR
PCIFR
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