ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 64

• Manufacturer Part Number: ATmega88
• Manufacturer: Atmel Corporation

Specifications of ATmega88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.4.1
12.5
12.5.1
2545T–AVR–05/11
Register description
Moving interrupts between application and boot space, Atmel ATmega88 and Atmel ATmega168
MCUCR – MCU control register
The MCU control register controls the placement of the interrupt vector table.
• Bit 1 – IVSEL: Interrupt vector select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the boot
loader section of the flash. The actual address of the start of the boot flash section is determined
by the BOOTSZ fuses. Refer to the section
gramming, Atmel ATmega88 and Atmel ATmega168” on page 269
unintentional changes of interrupt vector tables, a special write procedure must be followed to
change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the status
register is unaffected by the automatic disabling.
Note:
This bit is not available in Atmel ATmega48.
Bit
0x35 (0x55)
Read/write
Initial value
Address Labels Code
;
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C32
;
0x1C33
0x1C34
0x1C35
0x1C36
0x1C37
0x1C38
a. Write the interrupt vector change enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
If interrupt vectors are placed in the boot loader section and boot lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed
in the Application section and boot lock bit BLB12 is programmed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269
Boot Lock bits.
RESET: ldi
R
7
–
0
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
R
6
–
0
RESET
EXT_INT0
EXT_INT1
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
R
5
–
0
PUD
R/W
4
0
“Boot loader support – Read-while-write self-pro-
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
R
3
–
0
ATmega48/88/168
“Boot loader support – Read-while-
R
2
–
0
IVSEL
R/W
1
0
for details. To avoid
IVCE
R/W
for details on
0
0
MCUCR
64