ATtiny13A Atmel Corporation, ATtiny13A Datasheet - Page 161

• Manufacturer Part Number: ATtiny13A
• Manufacturer: Atmel Corporation

Specifications of ATtiny13A

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8126E–AVR–07/10
Mnemonics
BREAK
MOVW
SLEEP
SWAP
BSET
BCLR
PUSH
ROR
MOV
WDR
ASR
SEC
CLC
SEN
CLN
SES
SEV
SEH
CLH
LDD
LDD
STD
STD
LPM
LPM
LPM
SPM
OUT
POP
NOP
BST
BLD
SEZ
CLZ
CLS
CLV
SET
CLT
LDS
STS
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, b
Rd, k
X, Rr
Y, Rr
P, Rr
Rr, b
Z, Rr
k, Rr
Rd
Rd
Rd
Rd
Rr
s
s
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Load Direct from SRAM
Global Interrupt Disable
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Set Negative Flag
Clear T in SREG
Watchdog Reset
Description
Load Immediate
Clear Zero Flag
Set T in SREG
Swap Nibbles
Set Zero Flag
Store Indirect
No Operation
Load Indirect
Load Indirect
Load Indirect
Store Indirect
Store Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Break
Sleep
(see specific descr. for Sleep function)
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
(see specific descr. for WDR/Timer)
Rd(n) ← Rd(n+1), n=0..6
For On-chip Debug Only
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
Z ← Z - 1, Rd ← (Z)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
(Z) ← Rr, Z ← Z + 1
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
Operation
SREG(s) ← 1
SREG(s) ← 0
Rd ← STACK
STACK ← Rr
Rd ← (Y + q)
Rd ← (Z + q)
(Y + q) ← Rr
(Z + q) ← Rr
(z) ← R1:R0
Rd(b) ← T
T ← Rr(b)
Rd ← (X)
Rd ← (Y)
Rd ← (k)
Rd ← (Z)
R0 ← (Z)
Rd ← (Z)
Rd ← Rr
Rd ← K
(X) ← Rr
(Y) ← Rr
(Z) ← Rr
(k) ← Rr
Rd ← P
P ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
S ← 1
S ← 0
V ← 1
V ← 0
H ← 1
H ← 0
Z ← 1
Z ← 0
T ← 1
T ← 0
I ← 1
I ← 0
SREG(s)
SREG(s)
Flags
Z,C,N,V
Z,C,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
#Clocks
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
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