ATtiny13A Atmel Corporation, ATtiny13A Datasheet - Page 26

• Manufacturer Part Number: ATtiny13A
• Manufacturer: Atmel Corporation

Specifications of ATtiny13A

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.2.3
6.2.4
6.3
26
System Clock Prescaler
ATtiny13A
Internal 128 kHz Oscillator
Default Clock Source
When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in
Table
Table 6-5.
Notes:
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency depends on supply voltage, temperature and batch variations. This clock may be select
as the system clock by programming the CKSEL fuses to “11”.
When this clock source is selected, start-up times are determined by the SUT fuses as shown in
Table
Table 6-6.
Note:
The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest start-
up time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
The ATtiny13A system clock can be divided by setting the
on page
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
SUT[1:0]
SUT[1:0]
10
00
01
00
01
10
11
11
(1)
6-5.
6-6.
1. The device is shipped with this option selected.
2. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
28. This feature can be used to decrease power consumption when the requirement for
ensure programming mode can be entered.
ensure programming mode can be entered.
Power-down and Power-save
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Times for the 128 kHz Internal Oscillator
from Power-down
Start-up Time from
Start-up Time
6 CK
6 CK
6 CK
6 CK
6 CK
6 CK
Table 6-8 on page
Additional Delay from
Reset (V
14CK + 64 ms
14CK + 4 ms
Additional Delay
Reserved
Reserved
14CK + 64 ms
14CK
14CK + 4 ms
from Reset
CC
14CK
28.
(2)
= 5.0V)
(1)
“CLKPR – Clock Prescale Register”
I/O
, clk
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
ADC
, clk
Recommended
CPU
Usage
8126E–AVR–07/10
, and clk
FLASH