ATtiny13A Atmel Corporation, ATtiny13A Datasheet - Page 46

• Manufacturer Part Number: ATtiny13A
• Manufacturer: Atmel Corporation

Specifications of ATtiny13A

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
9.2.1
9.2.2
46
External Interrupts
ATtiny13A
Low Level Interrupt
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT0 pin or any of the PCINT[5:0] pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT[5:0] pins are configured as
outputs. This feature provides a way of generating a software interrupt. Pin change interrupts
PCI will trigger if any enabled PCINT[5:0] pin toggles. The PCMSK Register control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT[5:0] are detected asyn-
chronously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held
low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an
I/O clock, described in
A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in
“System Clock and Clock Options” on page
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction fol-
lowing the SLEEP command.
An example of timing of a pin change interrupt is shown in
Figure 9-1.
Timing of pin change interrupts
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCINT(0)
“Clock Systems and their Distribution” on page
PCIF
clk
clk
LE
pin_lat
D
Q
pin_sync
PCINT(0) in PCMSK(x)
23.
pcint_in_(0)
0
x
clk
Figure 9-1
pcint_syn
pcint_setflag
below.
23.
PCIF
8126E–AVR–07/10