EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet - Page 22

• Manufacturer Part Number: EP4SGX180FF35C4N
• Description: IC STRATIX IV FPGA 180K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Stratix® IV GXr

Specifications of EP4SGX180FF35C4N

• Number Of Logic Elements/cells: 175750
• Number Of Labs/clbs: 7030
• Total Ram Bits: 13954048
• Number Of I /o: 564
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–22. Differential I/O Standard Specifications
December 2011 Altera Corporation
PCML
2.5 V
LVDS
(HIO)
2.5 V
LVDS
(VIO)
RSDS
(HIO)
RSDS
(VIO)
Mini-LVDS
(HIO)
Mini-LVDS
(VIO)
LVPECL
Notes to
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in
(3) RL range: 90
(4) The receiver voltage input range for the data rate when D
(5) The receiver voltage input range for the data rate when D
Standard
I/O
The receiver voltage input range for the data rate when D
The receiver voltage input range for the data rate when D
Table
Power Consumption
transmitter, receiver, and reference clock I/O pin specifications, refer to
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 200
2.375 2.5 2.625 200
2.375 2.5 2.625 300
2.375 2.5 2.625 300
1–22:
Min
f
1

Transmitter, receiver, and input reference clock pins of high-speed transceivers use PCML I/O standard. For
RL
V
CCIO

Typ
110  .
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
For more information about power estimation tools, refer to the
Estimator User Guide
Handbook.
(V)
Max
Min Condition Max Min
V
1.25 V
1.25 V
1.25 V
1.25 V
V
V
V
V
ID
CM
CM
CM
CM
—
—
—
—
(mV)
=
=
=
=
and the
MAX
MAX
MAX
MAX
600
600
—
—
—
—
—
—
—
—
(Note
> 700 Mbps is 1.0 V  V
 700 Mbps is zero V  V
> 700 Mbps is 0.85 V  V
 700 Mbps is 0.45 V  V
PowerPlay Power Analysis
0.05
1.05
0.05
1.05
0.3
0.3
0.4
0.4
0.6
(4)
(4)
(5)
(5)
1),
1
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
page
(2)
Condition
700 Mbps
700 Mbps
700 Mbps
“Transceiver Performance Specifications” on page
V
ICM(DC)
D
D
D
®
MAX
MAX
MAX
1–24.
—
—
—
—
—
—
—
II PowerPlay Power Analyzer feature.
>
>
>
(V)
IN
IN
IN
IN
 1.6 V.
 1.85 V.
 1.75 V.
 1.95 V.
1.325
1.325
1.55
1.55
Max
1.8
1.8
1.4
1.4
1.8
1.6
(4)
(4)
(5)
(5)
Table 1–23 on page 1–15
chapter in the Quartus II
0.247
0.247
0.247
0.247
0.25
0.25
Min
0.1
0.1
—
—
V
OD
(V)
Typ Max
0.2
0.2
—
—
—
—
—
—
—
—
PowerPlay Early Power
(3)
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
—
—
1.125 1.25 1.375
1.125 1.25 1.375
Min
0.5
0.5
—
—
and
1–15.
1
1
1
1
V
OCM
Table 1–24 on
1.25
1.25
Typ
1.2
1.2
1.2
1.2
—
—
(V)
1–14
(3)
Max
1.5
1.5
1.4
1.5
1.4
1.5
—
—