EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet - Page 51

• Manufacturer Part Number: EP4SGX180FF35C4N
• Description: IC STRATIX IV FPGA 180K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Stratix® IV GXr

Specifications of EP4SGX180FF35C4N

• Number Of Logic Elements/cells: 175750
• Number Of Labs/clbs: 7030
• Total Ram Bits: 13954048
• Number Of I /o: 564
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices
December 2011 Altera Corporation
Sinusoidal Jitter
tolerance at 3072 Mbps
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(6) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(7) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(8) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(9) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(10) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(11) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(12) The fibre channel transmitter jitter generation numbers are compliant to the specification at 
(13) The fibre channel receiver jitter tolerance numbers are compliant to the specification at 
(14) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(15) Stratix IV PCIe receivers are compliant to this specification provided the V
(16) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(17) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(18) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Description
Table
Symbol/
1–30:
Jitter Frequency = 21.8
KHz
Pattern = CJPAT
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
Conditions
Min Typ
–2 Commercial
Speed Grade
> 8.5
> 0.1
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
TX-CM-DC-ACTIVEIDLE-DELTA
Max
and –2× Commercial
Min
Industrial/Military
–3 Commercial/
Speed Grade
R
interoperability point.
(Note
> 8.5
> 0.1
Typ
T
interoperability point.
of the upstream transmitter is less than 50mV.
1),
Max
(2)
(Part 9 of 9)
Min Typ
Industrial Speed
–4 Commercial/
Grade
> 8.5
> 0.1
Max
Unit
1–43
UI
UI