EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet - Page 31

• Manufacturer Part Number: EP4SGX180FF35C4N
• Description: IC STRATIX IV FPGA 180K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Stratix® IV GXr

Specifications of EP4SGX180FF35C4N

• Number Of Logic Elements/cells: 175750
• Number Of Labs/clbs: 7030
• Total Ram Bits: 13954048
• Number Of I /o: 564
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 9 of 9)
December 2011 Altera Corporation
Digital reset pulse
width
Notes to
(1) The
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) You must use the 1.1-V RX V
(7) The rate matcher supports only up to
(8) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to
(9) Time for which the CDR must be kept in lock-to-reference (LTR) mode after rx_pll_locked goes high and before rx_locktodata is asserted
(10) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to
(11) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the "Left/Right
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in
(15) Pending Characterization.
(16) The Quartus II software automatically selects the appropriate /L divider depending on the configured data.
(17) The maximum transceiver-FPGA fabric interface speed of 265.625 MHz is allowed only in Basic low-latency PCS mode with a 32-bit interface
(18)
(19) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx)
(20) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
(21) The rise and fall time transition is specified from 20% to 80%.
(22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These
Description
EP4SGX110FF35, EP4SGX230DF29, EP4SGX110FF35, EP4SGX180DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX180FF35,
EP4SGX290FH29, EP4SGX360FF35, and EPSGX360FH29.
rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more
information, refer to the
in manual mode. Refer to
PLL Requirements in Basic (PMA Direct) Mode" section in the
the link. You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about
clocking requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the
chapter.
width. For more information, refer to the “Basic Double-Width Mode Configurations” section in the
chapter.
Figure 1–1
channels physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig
instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the
Symbol/
–
Table
2× speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29,
1–23:
shows the AC gain curves for each of the 16 available equalization settings.
Dynamic Reconfiguration in Stratix IV Devices
Conditions
Figure 1–2 on page
ICM
—
setting if the input serial data standard is LVDS.
±
300 parts per million (ppm).
Min
1–32.
–2 Commercial
Speed Grade
Typ
Transceiver Clocking in Stratix IV Devices
Max
Minimum is two parallel clock cycles
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
chapter.
Industrial/Military and
Min
–2× Commercial
Speed Grade
–3 Commercial/
Transceiver Architecture in Stratix IV Devices
Typ
Figure 1–2 on page
(1)
Max
Transceiver Architecture in Stratix IV Devices
Transceiver Clocking in Stratix IV Devices
Commercial/Industrial
Figure 1–2 on page
Min
Figure 1–3 on page
chapter.
Speed Grade
1–32.
Typ
–4
1–32.
Max
1–32.
chapter.
Unit
—
1–23