EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet - Page 60

• Manufacturer Part Number: EP4SGX180FF35C4N
• Description: IC STRATIX IV FPGA 180K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Stratix® IV GXr

Specifications of EP4SGX180FF35C4N

• Number Of Logic Elements/cells: 175750
• Number Of Labs/clbs: 7030
• Total Ram Bits: 13954048
• Number Of I /o: 564
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

1–52
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Configuration and JTAG Specifications
Table 1–37
Table 1–37. Configuration Mode Specifications for Stratix IV Devices—Preliminary
Table 1–38
Table 1–38. JTAG Timing Parameters and Values for Stratix IV Devices—Preliminary
Temperature Sensing Diode Specifications
Table 1–39
Table 1–39. External Temperature Sensing Diode Specifications—Preliminary
Passive serial
Fast passive parallel
Fast active serial
Remote update only in fast AS mode
Note to
(1) This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for
t
t
t
t
t
t
t
t
t
Note to
(1) A 1 ns adder is required for each V
I
V
Series resistance
Diode ideality factor
JCP
JCH
JCL
JPSU (TDI)
JPSU (TMS)
JPH
JPCO
JPZX
JPXZ
bias
bias,
Symbol
, diode source current
each device may vary depending on device density. For more information, refer to the
Security, and Remote System Upgrades in Stratix IV Devices
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
voltage across diode
Table
Table
lists the Stratix IV configuration mode specifications.
lists the JTAG timing parameters and values for Stratix IV devices.
lists the specifications for the Stratix IV temperature sensing diode.
1–37:
1–38:
Programming Mode
Description
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
(1)
CCIO
Description
voltage step down from 3.0 V. For example, t
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Min
0.3
—
—
8
Min
4.3
—
—
17
chapter.
DCLK F
Typ
—
—
—
—
Typ
5.3
—
—
26
Min
30
14
14
—
—
—
1
3
5
December 2011 Altera Corporation
MAX
JPCO
Configuration, Design
= 12 ns if V
11
14
14
1.030
Switching Characteristics
Max
Max
500
125
125
Max
0.9
< 5
40
10
—
—
—
—
—
—
(1)
(1)
(1)
CCIO
of the TDO
MHz
MHz
MHz
MHz
Unit
Unit
Unit
A
—
ns
ns
ns
ns
ns
ns
ns
ns
ns

V