EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet - Page 64

• Manufacturer Part Number: EP4SGX180FF35C4N
• Description: IC STRATIX IV FPGA 180K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Stratix® IV GXr

Specifications of EP4SGX180FF35C4N

• Number Of Logic Elements/cells: 175750
• Number Of Labs/clbs: 7030
• Total Ram Bits: 13954048
• Number Of I /o: 564
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

1–56
Table 1–42. DPA Lock Time Specifications—Stratix IV ES Devices Only
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
SPI-4
Parallel Rapid
I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to commercial, industrial, and military speed grades.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Standard
Table 1–42
00000000001111111111
:
Training Pattern
Table 1–42
Figure 1–4
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
00001111
10010000
10101010
01010101
rx_dpa_locked
rx_reset
lists the DPA lock time specifications for Stratix IV ES devices.
shows the DPA lock time specifications with DPA PLL calibration enabled.
Number of Data
one repetition
Transitions in
of training
pattern
2
2
4
8
8
transitions
256 data
repetitions
transitions
Number of
per 256
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
clock cycles
data
128
128
96 slow
64
32
32
(4)
(Note
DPA Lock Time
without DPA PLL
without DPA PLL
without DPA PLL
without DPA PLL
without DPA PLL
transitions
256 data
with DPA PLL
with DPA PLL
with DPA PLL
with DPA PLL
with DPA PLL
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
Condition
1), (2),
clock cycles
(3)
96 slow
December 2011 Altera Corporation
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
256 data transitions
256 data transitions
256 data transitions
256 data transitions
256 data transitions
transitions
256 data
Switching Characteristics
Maximum
(5)
(5)
(5)
(5)
(5)