STM8S103F3

Manufacturer Part NumberSTM8S103F3
DescriptionAccess line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM
ManufacturerSTMicroelectronics
STM8S103F3 datasheet
 


Specifications of STM8S103F3

Program Memory8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcyclesData Memory640 bytes true data EEPROM; endurance 300 kcycles
Ram1 KbytesAdvanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
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STM8S103K3 STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data
LQFP32 7x7
TSSOP20
SO20W 300 mils
Features
Core
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbytes Flash; data retention
20 years at 55 °C after 10 kcycles
Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
RAM: 1 Kbytes
Clock, reset and supply management
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
-
Low power crystal resonator oscillator
-
External clock input
-
Internal, user-trimmable 16 MHz RC
-
Internal low power 128 kHz RC
Clock security system with clock monitor
Power management:
-
Low power modes (wait, active-halt, halt)
-
Switch-off peripheral clocks individually
Permanently active, low consumption power-on
and power-down reset
July 2011
EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
UFQFPN32 5x5
Timers
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
UFQFPN20 3x3
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window watchdog and independent watchdog
timers
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
2
I
C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
Up to 28 I/Os on a 32-pin package including 21
high sink outputs
Highly robust I/O design, immune against current
injection
Development support
-
Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
Unique ID
96-bit unique key for each device
DocID15441 Rev 7
1/113
www.st.com

STM8S103F3 Summary of contents

  • Page 1

    ... STM8S103K3 STM8S103F3 STM8S103F2 Access line, 16 MHz STM8S 8-bit MCU Kbytes Flash, data LQFP32 7x7 TSSOP20 SO20W 300 mils Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline • Extended instruction set Memories • Program memory: 8 Kbytes Flash; data retention 20 years at 55 ° ...

  • Page 2

    ... Alternate function remapping .......................................................................................25 6 Memory and register map .....................................................................................26 6.1 Memory map ................................................................................................................26 6.2 Register map ...............................................................................................................27 6.2.1 I/O port hardware register map ............................................................27 6.2.2 General hardware register map ..........................................................28 6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................38 7 Interrupt vector mapping ......................................................................................40 8 Option bytes ...........................................................................................................42 8.1 Alternate function remapping bits ................................................................................44 2/113 STM8S103K3 STM8S103F3 STM8S103F2 DocID15441 Rev 7 ...

  • Page 3

    ... STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID ................................................................................................................47 10 Electrical characteristics ....................................................................................48 10.1 Parameter conditions .................................................................................................48 10.1.1 Minimum and maximum values .........................................................48 10.1.2 Typical values .....................................................................................48 10.1.3 Typical curves ....................................................................................48 10.1.4 Loading capacitor ...............................................................................48 10.1.5 Pin input voltage .................................................................................49 10.2 Absolute maximum ratings ........................................................................................49 10.3 Operating conditions ..................................................................................................51 10.3.1 VCAP external capacitor ....................................................................52 10.3.2 Supply current characteristics ............................................................53 10.3.3 External clock sources and timing characteristics .............................63 10.3.4 Internal clock sources and timing characteristics ...............................65 10 ...

  • Page 4

    ... Table 41. Output driving current (high sink ports) ..................................................................................72 Table 42. NRST pin characteristics ........................................................................................................77 Table 43. SPI characteristics ..................................................................................................................80 2 Table 44 characteristics ..................................................................................................................82 Table 45. ADC characteristics ................................................................................................................84 Table 46. ADC accuracy with R Table 47. ADC accuracy with R 4/113 STM8S103K3 STM8S103F3 STM8S103F2 = 5 V ............................................................ 3.3 V ......................................................... ............................................................. 3.3 V ..........................................................58 DD < ...

  • Page 5

    ... STM8S103K3 STM8S103F3 STM8S103F2 Table 48. EMS data ................................................................................................................................88 Table 49. EMI data .................................................................................................................................88 Table 50. ESD absolute maximum ratings .............................................................................................89 Table 51. Electrical sensitivities .............................................................................................................90 Table 52. 32-pin low profile quad flat package mechanical data ............................................................91 Table 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................93 Table 54. 20-lead, ultra thin, fine pitch quad flat no-lead package ( package mechanical data ....95 Table 55 ...

  • Page 6

    ... V (standard ports) ....................................................................... 3.3 V (standard ports) ................................................................... (high sink ports) ....................................................................... 3.3 V (high sink ports) .................................................................... temperatures ........................................................... temperatures ................................................. temperatures ......................................................79 DD (1) ................................................................................... bus and timing diagram ............................................................86 DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 = 16 MHz ............................................. .................................................... MHz .............................................. .....................................................63 ...

  • Page 7

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 48. 20-lead, plastic small outline (300 mils) package .................................................................97 Figure 49. Recommended footprint for on-board emulation ..................................................................98 Figure 50. Recommended footprint without on-board emulation ...........................................................99 Figure 51. STM8S103x access line ordering information scheme ......................................................102 DocID15441 Rev 7 List of figures 7/113 ...

  • Page 8

    ... For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). • For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). 8/113 STM8S103K3 STM8S103F3 STM8S103F2 DocID15441 Rev 7 ...

  • Page 9

    ... STM8S103K3 STM8S103F3 STM8S103F2 2 Description The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost. ...

  • Page 10

    ... Clock controller Reset Detector BOR Clock to peripherals and core STM8 core SPI UART1 ADC1 Beeper DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 XTAL 1-16 MHz RC int. 16 MHz RC int. 128 kHz Window WDG Independent WDG 8 Kbytes program Flash 640 bytes data EEPROM 1 Kbyte RAM ...

  • Page 11

    ... STM8S103K3 STM8S103F3 STM8S103F2 4 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. ...

  • Page 12

    ... The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: • Main program memory Kbytes minus UBC • User-specific boot code (UBC): Configurable Kbytes 12/113 STM8S103K3 STM8S103F3 STM8S103F2 DocID15441 Rev 7 ...

  • Page 13

    ... STM8S103K3 STM8S103F3 STM8S103F2 The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines ...

  • Page 14

    ... Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. 14/113 STM8S103K3 STM8S103F3 STM8S103F2 Peripheral Bit Peripheral clock clock ...

  • Page 15

    ... STM8S103K3 STM8S103F3 STM8S103F2 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer ...

  • Page 16

    ... Any integer TIM1 16 from 1 to 65536 Any power of TIM2 16 2 from 1 to 32768 Any power of TIM4 8 2 from 1 to 128 16/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 3: TIM timer features Counting CAPCOM Complem. mode channels outputs Up/down DocID15441 Rev 7 Timer Ext ...

  • Page 17

    ... STM8S103K3 STM8S103F3 STM8S103F2 4.13 Analog-to-digital converter (ADC1) The STM8S003xx products contain a 10-bit successive approximation A/D converter (ADC1) with external multiplexed inputs channels and the following features: The STM8S103xx family products contain a 10-bit successive approximation A/D converter (ADC1) with external multiplexed input channels and the following main features: • ...

  • Page 18

    ... Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) 18/113 STM8S103K3 STM8S103F3 STM8S103F2 /16) CPU /2) both for master and slave MASTER DocID15441 Rev 7 ...

  • Page 19

    ... STM8S103K3 STM8S103F3 STM8S103F2 5 Pinout and pin description Type Level Output speed Port and control configuration Reset state 5.1 STM8S103Kx UFQFPN32/LQFP32 pinout and pin description Table 4: Legend/abbreviations for pinout tables I= Input Output Power supply CM = CMOS Input Output HS = High sink O1 = Slow ( MHz Fast ( MHz) ...

  • Page 20

    ... PF4 I PB7 I PB6 I PB5/ I C_SDA I PB4/ I C_SCL I PB3/AIN3/ I/O X TIM1_ETR 14 PB2/AIN2/ I/O X TIM1_CH3N 20/113 STM8S103K3 STM8S103F3 STM8S103F2 Output Ext. High wpu Speed OD (1) interrupt sink (3) ...

  • Page 21

    ... STM8S103K3 STM8S103F3 STM8S103F2 Input Pin Pin Type no. name floating 15 PB1/AIN1/ I/O X TIM1_CH2N 16 PB0/AIN0/ I/O X TIM1_CH1N 17 PE5/ I/O X SPI_NSS 18 PC1/ I/O X TIM1_CH1/ UART1_CK 19 PC2/ I/O X TIM1_CH2 20 PC3/ I/O X TIM1_CH3 21 PC4/ I/O X TIM1_CH4/ CLK_CCO 22 PC5/ SPI_SCK I PC6/ PI_MOSI I PC7/ PI_MISO I PD0/ I/O X TIM1_BKIN [CLK_CCO] 26 PD1/ SWIM I/O X (4) 27 PD2 ...

  • Page 22

    ... In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode are not implemented). (4) The PD1 pin is in input pull-up during the reset phase and after internal reset release. 5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description 5.2.1 STM8S103Fx TSSOP20/SO20 pinout 22/113 STM8S103K3 STM8S103F3 STM8S103F2 Output Ext. High wpu Speed OD (1) interrupt sink ...

  • Page 23

    ... STM8S103K3 STM8S103F3 STM8S103F2 1. HS high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 5.2.2 STM8S103Fx UFQFPN20 pinout OSCIN/PA1 OSCOUT/PA2 1. HS high sink capability. ...

  • Page 24

    ... CH1 PC7/ SPI_MISO [TIM1_ CH2 PD1/ SWIM 19 16 PD2/AIN3/[TIM2_ CH3 PD3/ AIN4/ TIM2_ CH2/ ADC_ ETR 24/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 6: STM8S103Fx pin description Input Output Type Ext. High sink floating wpu Speed (1) interr. I ...

  • Page 25

    ... STM8S103K3 STM8S103F3 STM8S103F2 (1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. (2) When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven ...

  • Page 26

    ... Memory and register map 6 Memory and register map 6.1 Memory map 26/113 STM8S103K3 STM8S103F3 STM8S103F2 Figure 6: Memory map 0x00 0000 RAM (1 Kbyte) 513 bytes stack 0x00 03FF 0x00 0800 Reserved 0x00 3FFF 0x00 4000 640 bytes data EEPROM 0x00 427F 0x00 4280 ...

  • Page 27

    ... STM8S103K3 STM8S103F3 STM8S103F2 6.2 Register map 6.2.1 I/O port hardware register map Address Block 0x00 5000 0x00 5001 0x00 5002 Port A 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 Port B 0x00 5008 0x00 5009 0x00 500A 0x00 500B 0x00 500C Port C 0x00 500D ...

  • Page 28

    ... Flash control register 2 FLASH_NCR2 Flash complementary control register 2 FLASH _FPR Flash protection register FLASH _NFPR Flash complementary protection register FLASH _IAPSR Flash in-application programming status register DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 Reset status 0x00 0x00 (1) 0xXX 0x00 0x00 0x00 Reset status 0x00 ...

  • Page 29

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5062 Flash 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to Reserved area (59 bytes) 0x00 509F 0x00 50A0 ITC 0x00 50A1 0x00 50A2 to Reserved area (17 bytes) 0x00 50B2 0x00 50B3 RST 0x00 50B4 to Reserved area (12 bytes) ...

  • Page 30

    ... Reserved area (13 bytes) 0x00 50EF 0x00 50F0 AWU 0x00 50F1 0x00 50F2 0x00 50F3 BEEP 30/113 STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name CLK_CCOR Configurable clock control register CLK_PCKENR2 Peripheral clock gating register 2 CLK_HSITRIMR HSI clock calibration trimming register ...

  • Page 31

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 50F4 to Reserved area (12 bytes) 0x00 50FF 0x00 5200 SPI 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to Reserved area (8 bytes) 0x00 520F 2 0x00 5210 I C 0x00 5211 ...

  • Page 32

    ... UART1 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 32/113 STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name 2 I2C_SR2 I C status register 2 2 I2C_SR3 I C status register 3 2 I2C_ITR ...

  • Page 33

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 523B to Reserved area (21 bytes) 0x00 523F 0x00 5250 TIM1 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D ...

  • Page 34

    ... Reserved area (147 bytes) 0x00 52FF 0x00 5300 TIM2 34/113 STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name TIM1_CNTRL TIM1 counter low TIM1_PSCRH TIM1 prescaler register high TIM1_PSCRL TIM1 prescaler register low TIM1_ARRH ...

  • Page 35

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F 0x00 5310 0x00 5311 Register label ...

  • Page 36

    ... Reserved area (153 bytes) 0x00 53DF 0x00 53E0 to ADC1 0x00 53F3 0x00 53F4 to Reserved area (12 bytes) 0x00 53FF 36/113 STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name TIM2_CCR1L TIM2 capture/compare register 1 low TIM2_CCR2H TIM2 capture/compare reg. 2 high TIM2_CCR2L TIM2 capture/compare register 2 low ...

  • Page 37

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 5400 ADC1 0x00 5401 0x00 5402 0x00 5403 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 0x00 5409 0x00 540A 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F Register label Register name ...

  • Page 38

    ... CPU 0x00 7F70 0x00 7F71 0x00 7F72 ITC 0x00 7F73 0x00 7F74 38/113 STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name Register label Register name A Accumulator PCE Program counter extended PCH Program counter high PCL ...

  • Page 39

    ... STM8S103K3 STM8S103F3 STM8S103F2 Address Block 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 0x00 7F80 SWIM 0x00 7F81 to 0x00 7F8F 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 DM 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 ...

  • Page 40

    ... Reserved 17 UART1 Tx complete 18 UART1 Receive register DATA FULL interrupt 20 Reserved 21 Reserved 22 ADC1 end of conversion/ analog ADC1 watchdog interrupt 40/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 10: Interrupt mapping Wakeup from halt mode Yes - - - - (1) Yes Yes Yes Yes Yes - - Yes - - - - - ...

  • Page 41

    ... STM8S103K3 STM8S103F3 STM8S103F2 IRQ Source Description no. block 23 TIM4 TIM4 update/ overflow 24 Flash EOP/WR_PG_DIS (1) Except PA1 Wakeup from halt mode - - Reserved DocID15441 Rev 7 Interrupt vector mapping Wakeup from Vector address active-halt mode - 0x00 8064 - 0x00 8068 0x00 806C to 0x00 807C 41/113 ...

  • Page 42

    ... Clock OPT4 Reserved option 0x4808 NOPT4 Reserved 0x4809 HSE clock OPT5 HSECNT [7:0] startup 0x480A NOPT5 NHSECNT [7:0] Option byte no. OPT0 42/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 11: Option bytes AFR5 AFR4 AFR3 AFR6 NAFR6 NAFR5 NAFR4 NAFR3 HSI LSI_ EN TRIM NHSI NLSI_ ...

  • Page 43

    ... STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. OPT1 OPT2 OPT3 Description Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 defined as UBC, memory write-protected 0x02: Pages defined as UBC, memory write-protected. ...

  • Page 44

    ... Alternate function remapping bits Table 13: STM8S103K alternate function remapping bits for 32-pin devices Option byte no. OPT2 44/113 STM8S103K3 STM8S103F3 STM8S103F2 Description 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN ...

  • Page 45

    ... STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. (1) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. (2) Refer to pinout description. Table 14: STM8S103F alternate function remapping bits for 20-pin devices Option byte no. OPT2 (1) Description 1: Port D0 alternate function = CLK_CCO. ...

  • Page 46

    ... Option byte no. (1) Refer to pinout description. (2) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. 46/113 STM8S103K3 STM8S103F3 STM8S103F2 Description Reserved AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate (1) functions . 1: Port A3 alternate function = SPI_NSS ...

  • Page 47

    ... STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm ...

  • Page 48

    ... Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. 48/113 STM8S103K3 STM8S103F3 STM8S103F2 °C and ° Figure 7: Pin loading conditions ...

  • Page 49

    ... STM8S103K3 STM8S103F3 STM8S103F2 10.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied ...

  • Page 50

    ... DD ground lines (sink) SS (5) ) pins must always be connected to the external supply. SS while a negative injection is induced maximum current injection on four I/O port pins of the device. Table 18: Thermal characteristics DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 (1) Max (2) 100 ( ± 4 ± 4 ± 4 (5) ± ...

  • Page 51

    ... STM8S103K3 STM8S103F3 STM8S103F2 10.3 Operating conditions Symbol Parameter f Internal CPU clock frequency CPU V Standard operating voltage DD VCAP C : capacitance of EXT external capacitor ESR of external (1) capacitor ESL of external (1) capacitor ( Power dissipation at T for suffix 6 Power dissipation at T for suffix 3 T Ambient temperature for 6 suffix ...

  • Page 52

    ... A -40 to 125 ° 4.0 2.95 Conditions (1) V rising DD delay. The application must ensure that V TEMP min) when the t delay has elapsed. DD TEMP DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 (see Thermal characteristics JA given in Thermal characteristics. JA versus V DD 5.0 5.5 Supply voltage Min Typ Max 2 ∞ ...

  • Page 53

    ... STM8S103K3 STM8S103F3 STM8S103F2 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in 10.3.2.1 Total current consumption in run mode The MCU is placed under the following conditions: • All I/O pins in input mode with a static value at V • ...

  • Page 54

    ... DD(RUN) CPU 128 kHz f CPU 16 MHz Supply current in run mode, code executed f CPU from Flash 2 MHz f CPU 54/113 STM8S103K3 STM8S103F3 STM8S103F2 = f = MASTER HSI RC osc. (16 MHz/ /128 = MASTER HSI RC osc. (16 MHz /128 = MASTER HSI RC osc. (16 MHz/ MASTER LSI RC osc. (128 kHz) HSE crystal osc. (16 MHz) ...

  • Page 55

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions 128 = 125 kHz f CPU 128 = 15.625 kHz f CPU 128 kHz (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 Total current consumption in wait mode Table 23: Total current consumption in wait mode at V ...

  • Page 56

    ... HSI RC osc. CPU MASTER 15.625 kHz (16 MHz/ LSI RC osc. CPU MASTER 128 kHz (128 kHz) (3) Flash mode (2) Operating mode Operating mode Power-down mode Power-down mode DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 Typ Max 1.1 1.3 0.89 1.1 0.7 0.88 0.45 0.57 (2) 0.4 0. Max at 85 Typ °C Clock source (1) HSE crystal osc ...

  • Page 57

    ... STM8S103K3 STM8S103F3 STM8S103F2 Conditions Main Symbol Parameter voltage regulator (MVR) Supply current I in active halt DD(AH) mode Off Supply current I in active halt DD(AH) mode (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. ...

  • Page 58

    ... WU(AH) Wakeup time active halt mode to run (3) mode 58/113 STM8S103K3 STM8S103F3 STM8S103F2 Conditions Flash in operating mode, HSI clock after wakeup Flash in power-down mode, HSI clock after wakeup Conditions Flash in operating mode, HSI clock after wakeup Flash in power-down mode, HSI ...

  • Page 59

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Wakeup time active halt mode to run (3) mode Wakeup time active halt mode to run (3) mode Wakeup time from halt mode to run t WU(H) (3) mode (1) Data guaranteed by design, not tested in production 1/f WU(WFI) master (3) Measured from interrupt event to interrupt vector fetch. ...

  • Page 60

    ... Table 31: Peripheral current consumption (1) (1) (1) (2) (2) (2) (3) measurement between reset configuration and timer counter running DD measurement between the on-chip peripheral when kept under reset DD measurement between reset configuration and continuous A/D DD DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 Typ. 210 130 50 120 45 65 1000 Unit μA ...

  • Page 61

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 11: Typ I Figure 12: Typ I vs. V HSE user external clock, f DD(RUN) DD vs. f HSE user external clock, V DD(RUN) CPU DocID15441 Rev 7 Electrical characteristics = 16 MHz CPU = 61/113 ...

  • Page 62

    ... Electrical characteristics Figure 13: Typ I Figure 14: Typ I 62/113 STM8S103K3 STM8S103F3 STM8S103F2 vs. V HSI RC osc, f DD(RUN) DD vs. V HSE user external clock, f DD(WFI) DD DocID15441 Rev MHz CPU = 16 MHz CPU ...

  • Page 63

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 15: Typ I Figure 16: Typ I 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 32: HSE user external clock characteristics Symbol Parameter f User external clock source HSE_ext frequency (1) V OSCIN input pin high level ...

  • Page 64

    ... Figure 17: HSE external clocksource External clock source OSCIN Table 33: HSE oscillator characteristics Conditions Min pF MHz OSC pF, f =16 MHz OSC stabilized DD DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 f HSE STM8 Typ Max 16 220 20 6 (startup) (3) 1.6 (stabilized) 6 (startup) (3) 1.2 (stabilized) 1 Unit MHz kΩ mA/V ...

  • Page 65

    ... STM8S103K3 STM8S103F3 STM8S103F2 ( approximately equivalent crystal Cload. (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value. Refer to crystal manufacturer for more details m (3) Data based on characterization results, not tested in production. ( the start-up time measured from the moment it is enabled (by software stabilized 16 SU(HSE) MHz oscillation is reached ...

  • Page 66

    ... I HSI oscillator DD(HSI) power consumption (1) Refer to application note. (2) Data based on characterization results, not tested in production. (3) Guaranteed by design, not tested in production. 66/113 STM8S103K3 STM8S103F3 STM8S103F2 Conditions Min User-trimmed with CLK_HSITRIMR register for given V and (1) conditions ( 25°C ...

  • Page 67

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 19: Typical HSI frequency variation vs V Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Symbol Parameter f Frequency LSI t LSI oscillator wake-up time su(LSI) I LSI oscillator power consumption DD(LSI) Figure 20: Typical LSI frequency variation vs V and T DD ...

  • Page 68

    ... Erase/write cycles RW (program memory) Erase/write cycles (data memory) t Data retention (program RET and data memory) after 10k erase/write cycles +55 °C A 68/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 36: RAM and hardware registers Conditions (1) Halt mode (or reset) Conditions f ≤ 16 MHz CPU ( +85 ° +125 °C ...

  • Page 69

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Data retention (data memory) after 300k erase/write cycles +125 ° Supply current (Flash DD programming or erasing for 1 to 128 bytes) (1) Data based on characterization results, not tested in production. (2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte ...

  • Page 70

    ... Leakage current in adjacent I/O (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterisation results, not tested in production. Figure 21: Typical V Figure 22: Typical pull-up resistance vs V 70/113 STM8S103K3 STM8S103F3 STM8S103F2 Conditions Min V ≤ V ≤ Injection current ±4 mA ...

  • Page 71

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 23: Typical pull-up current vs V Symbol Parameter Output low level with 8 pins sunk V OL Output low level with 4 pins sunk Output high level with 8 pins sourced V OH Output high level with 4 pins sourced (1) Data based on characterization results, not tested in production ...

  • Page 72

    ... Output high level with 8 pins sourced Output high level with 4 pins sourced V OH Output high level with 4 pins sourced (1) Data based on characterization results, not tested in production 72/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 41: Output driving current (high sink ports) Figure 24: Typ (standard ports DocID15441 Rev 7 ...

  • Page 73

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 26: Typ. V Figure 25: Typ 3.3 V (standard ports (true open drain ports DocID15441 Rev 7 Electrical characteristics 73/113 ...

  • Page 74

    ... Electrical characteristics Figure 27: Typ. V 74/113 STM8S103K3 STM8S103F3 STM8S103F2 @ V = 3.3 V (true open drain ports Figure 28: Typ (high sink ports DocID15441 Rev 7 ...

  • Page 75

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 29: Typ Figure 30: Typ DocID15441 Rev 7 Electrical characteristics = 3.3 V (high sink ports (standard ports) DD 75/113 ...

  • Page 76

    ... Electrical characteristics Figure 31: Typ. V 76/113 - Figure 32: Typ DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 = 3.3 V (standard ports (high sink ports) DD ...

  • Page 77

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 33: Typ. V 10.3.7 Reset pin characteristics Subject to general operating conditions for V Symbol Parameter V IL(NRST) NRST input low (1) level voltage V IH(NRST) NRST input high level voltage V OL(NRST) NRST output low level voltage R PU(NRST) NRST pull-up (2) resistor t I FP(NRST) NRST input filtered ...

  • Page 78

    ... Data based on characterization results, not tested in production. (2) The R pull-up equivalent resistor is based on a resistive transistor PU (3) Data guaranteed by design, not tested in production. Figure 34: Typical NRST V Figure 35: Typical NRST pull-up resistance vs V 78/113 STM8S103K3 STM8S103F3 STM8S103F2 Conditions Min 20 and DocID15441 Rev 7 Typ ...

  • Page 79

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 36: Typical NRST pull-up current vs V The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V Table 42: NRST pin characteristics For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current ...

  • Page 80

    ... Slave mode Master mode Slave mode Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Master mode (after enable edge) DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 Min Max MASTER 70 t ...

  • Page 81

    ... STM8S103K3 STM8S103F3 STM8S103F2 (1) Parameters are given by selecting 10 MHz I/O output frequency. (2) Data characterization in progress. (3) Values based on design simulation and/or characterization results, and not tested in production. (4) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. ...

  • Page 82

    ... MS BIN t h(MI OUT t v(MO) 2 Table 44 characteristics Standard mode I (2) Min 4.7 4.0 250 (3) 0 4.0 4.7 DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 (1) t r(SCK) t f(SCK LSB OUT LSB OUT t h(MO Fast mode I (2) (2) Max Min Max 1.3 0.6 100 (4) ...

  • Page 83

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter t STOP condition setup time su(STO) t STOP to START condition time w(STO:ST A) (bus free) C Capacitive load for each bus line b ( must be at least 8 MHz to achieve max fast I MASTER (2) 2 Data based on standard I (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the ...

  • Page 84

    ... MHz ADC MHz ADC MHz ADC MHz ADC depend on programming. Table 46: ADC accuracy with R (2) (2) DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 Min Typ Max 0.75 0.5 7 3.5 2. max) can be charged/discharged AIN After the end of the sample time t S. < ...

  • Page 85

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter |E | Gain error Differential linearity error Integral linearity error L (1) Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input ...

  • Page 86

    ... It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I pin characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 86/113 STM8S103K3 STM8S103F3 STM8S103F2 Conditions MHz ADC (2) f ...

  • Page 87

    ... STM8S103K3 STM8S103F3 STM8S103F2 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer T curves Offset error: deviation between the first actual transition and the first ideal one Gain error: deviation between the last ideal transition and the last actual one. ...

  • Page 88

    ... This emission test is in line with the norm SAE IEC 61967-2 which specifies the board and the loading of each pin. Symbol Parameter Peak level S EMI 88/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 48: EMS data Conditions (HSI clock), conforming to IEC 61000-4 ...

  • Page 89

    ... STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter SAE EMI level (1) Data based on characterisation results, not tested in production. 10.3.11.4 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181 ...

  • Page 90

    ... Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 90/113 STM8S103K3 STM8S103F3 STM8S103F2 Table 51: Electrical sensitivities Conditions °C ...

  • Page 91

    ... STM8S103K3 STM8S103F3 STM8S103F2 11 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. 11.1 32-pin LQFP package mechanical data ...

  • Page 92

    ... Min D3 E 8.800 E1 6.800 0.450 L1 k 0.0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits 92/113 STM8S103K3 STM8S103F3 STM8S103F2 inches Typ Max Min 5.600 9.000 9.200 0.3465 7.000 7.200 0.2677 5.600 0.800 0.600 0.750 0.0177 1.000 3.5° ...

  • Page 93

    ... STM8S103K3 STM8S103F3 STM8S103F2 11.2 32-lead UFQFPN package mechanical data Figure 45: 32-lead, ultra thin, fine pitch quad flat no-lead package ( Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package recommended to connect and solder this backside pad to PCB ground ...

  • Page 94

    ... DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 (1) inches Min Typ 0.0071 0.0098 0.1909 0.1969 0.1260 0.1909 0.1969 0.1260 0.1358 0.0197 0.0118 0.0157 ddd 103_A0A5_ME Max 0 ...

  • Page 95

    ... STM8S103K3 STM8S103F3 STM8S103F2 Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package ( package Dim. mm Min 0.500 A1 0.000 0.500 L2 0.300 0.180 ddd 0.050 (1) Values in inches are converted from mm and rounded to 4 decimal digits. mechanical data inches Typ ...

  • Page 96

    ... Table 55: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. mm Min A A1 0.050 A2 0.800 b 0.190 c 0.090 D 6.400 E 6.200 E1 4.300 e L 0.450 L1 96/113 STM8S103K3 STM8S103F3 STM8S103F2 Figure 47: 20-pin, 4.40 mm body, 0.65 mm pitch Typ Max 1.200 0.150 1.000 1.050 0.300 0.200 6.500 6.600 6.400 6.600 4.400 4.500 0.650 ...

  • Page 97

    ... STM8S103K3 STM8S103F3 STM8S103F2 Dim. mm Min k 0.0° aaa (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.5 20-pin SO package mechanical data Figure 48: 20-lead, plastic small outline (300 mils) package Table 56: 20-lead, plastic small outline (300 mils) mechanical data Dim. mm Min A 2.350 A1 0 ...

  • Page 98

    ... Drawing is not to scale 98/113 Typ Max 10.650 0.750 1.270 8.0° 0.100 0.5mm 4mm [0.157"] 1.65mm [0.065"] 0.3mm [0.012"] 4mm [0.157"] Bottom view DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 (1) inches Min Typ 0.3937 0.0098 0.0157 0.0° 0.8mm [0.032"] 0.5mm 0.9mm [0.035"] ai15319 Max 0.4193 ...

  • Page 99

    ... STM8S103K3 STM8S103F3 STM8S103F2 Figure 50: Recommended footprint without on-board emulation 1. Drawing is not to scale 2. Dimensions are in millimeters DocID15441 Rev 7 Package information 99/113 ...

  • Page 100

    ... I/Omax andV , expressed in Watts. This is the maximum chip internal DD DD =Σ Σ(( Table 57: Thermal characteristics (1) DocID15441 Rev 7 STM8S103K3 STM8S103F3 STM8S103F2 + P ) INTmax I/Omax ), taking into account the actual V Value and Unit °C/W °C/W ° ...

  • Page 101

    ... STM8S103K3 STM8S103F3 STM8S103F2 12.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application ...

  • Page 102

    ... For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 13.1 STM8S103 FASTROM microcontroller option list (last update: April 2010) Customer 102/113 STM8S103K3 STM8S103F3 STM8S103F2 Example: STM8 S Product class STM8 microcontroller Family type S = Standard ...

  • Page 103

    ... Padding value for unused program memory (check only one option) [ ]0xFF [ ]0x83 [ ]0x75 a FASTROM code name is assigned by STMicroelectronics. ............................................................................................. ............................................................................................. ............................................................................................. a ............................................................................................. 4 Kbyte [ ] STM8S103F2 [ ] STM8S103F2 [ ] STM8S103F2 Fixed value TRAP instruction opcode Illegal opcode (causes a reset when executed) DocID15441 Rev 7 Ordering information 8 Kbyte [ ] STM8S103K3 [ ] STM8S103F3 [ ] STM8S103K3 [ ] STM8S103F3 [ ] STM8S103F3 103/113 ...

  • Page 104

    ... OPT2 alternate function remapping for STM8S103K Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. AFR0 AFR1 (check only one option) AFR2 AFR3 AFR4 104/113 STM8S103K3 STM8S103F3 STM8S103F2 [ ] 0: Reset [ ] 1: Set [ ] 0: Reset [ ] 1: Set [ ] 0: Reset [ ] 1: Set [ ] 0: Reset [ ] 1: Set [ ] 0: Reset ...

  • Page 105

    ... STM8S103K3 STM8S103F3 STM8S103F2 AFR5 (check only one option) AFR6 (check only one option) AFR7 OPT2 alternate function remapping for STM8S103F Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. AFR0 (check only one option) ...

  • Page 106

    ... Comments: Supply operating range in the application: Notes: Date: Signature: 106/113 STM8S103K3 STM8S103F3 STM8S103F2 [ ] 1: Reset generated on halt if WWDG active [ ] 0: WWDG activated by software [ ] 1: WWDG activated by hardware [ ] 0: IWDG activated by software [ ] 1: IWDG activated by hardware [ ] 0: LSI clock is not available as CPU clock source [ ] 1: LSI clock is available as CPU clock source ...

  • Page 107

    ... STM8S103K3 STM8S103F3 STM8S103F2 14 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer ...

  • Page 108

    ... ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. 108/113 STM8S103K3 STM8S103F3 STM8S103F2 DocID15441 Rev 7 ...

  • Page 109

    ... STM8S103K3 STM8S103F3 STM8S103F2 15 Revision history Date Revision 02-Mar-2009 10-Apr-2009 10-Jun-2009 Table 58: Document revision history Changes 1 Initial revision 2 Added Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. Updated Auto wakeup Modified description of PB4 and PB5 (removed column) and added footnote concerning HS I/Os in VFQFPN32/LQFP32 ...

  • Page 110

    ... Revision history Date Revision 16-Oct-2009 22-Apr-2010 110/113 STM8S103K3 STM8S103F3 STM8S103F2 Changes Updated Table 19: General operating Updated name of Figure. Typical HSI accuracy at VDD = temperatures. Updated Table 43: SPI characteristics Added max values to Table 46: ADC accuracy with RAIN < 10 kΩ , VDD and Table 47: ADC accuracy with RAIN < ...

  • Page 111

    ... STM8S103K3 STM8S103F3 STM8S103F2 Date Revision 09-Sep-2010 12-Jul-2011 Changes Updated maximum power dissipation in operating conditions. Updated Θ in Table 57: Thermal JA Replaced package pitch digit by VFQFPN/UFQFPN package digit in Figure 51: STM8S103x access line ordering information scheme, and removed note 1. 6 Removed VFQFPN32 package. Removed internal reference voltage from converter (ADC1) ...

  • Page 112

    ... Revision history Date Revision 112/113 STM8S103K3 STM8S103F3 STM8S103F2 Changes Added note for Px_IDR registers in register map. Added recommendation concerning NRST pin level, and power consumption sensitive applications, above Recommended reset pin protection. Removed typical HSI accuracy curve in and timing characteristics. Renamed package type 2 into package pitch and added pitch code " ...

  • Page 113

    ... STM8S103K3 STM8S103F3 STM8S103F2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...