STM8S103F3

Manufacturer Part NumberSTM8S103F3
DescriptionAccess line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM
ManufacturerSTMicroelectronics
STM8S103F3 datasheet
 


Specifications of STM8S103F3

Program Memory8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcyclesData Memory640 bytes true data EEPROM; endurance 300 kcycles
Ram1 KbytesAdvanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
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STM8S103K3 STM8S103F3 STM8S103F2
Date
Revision
09-Sep-2010
12-Jul-2011
Changes
Updated maximum power dissipation in
operating
conditions.
Updated Θ
in
Table 57: Thermal
JA
Replaced package pitch digit by VFQFPN/UFQFPN package
digit in
Figure 51: STM8S103x access line ordering information
scheme, and removed note 1.
6
Removed VFQFPN32 package.
Removed internal reference voltage from
converter
(ADC1).
Updated "reset state" of
pinout tables
in
Pinout and pin
Added footnote to PD1/SWIM pin in
UFQFPN32/LQFP32 pinout and pin
Updated pins 14 and 19 (TSSOP20/SO20) / pins 11 and 16
(UFQFPN20) in
STM8S103Fx TSSOP20/SO20/UFQFPN20
pin
description.
General hardware register map
values; updated the reset state values of the RST_SR,
CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR,
and ADC_DRx registers in the "General hardware register
map" table.
Updated AFR2 description of OPT 2 in
alternate function remapping bits for 20-pin
Replaced 0.01 µF with 0.1 µf in
reset pin
protection.
Added "Typical application with I
I2C interface
characteristics.
Updated footnote 1 in
10 kΩ , VDD= 5 V
and
10 kΩ RAIN, VDD = 3.3 V
STM8S103 FASTROM microcontroller option
"special marking" section and AFR2 description of
alternate function remapping for
32-lead UFQFPN package mechanical
footnote and added three additional footnotes.
7
Updated note related to true open-drain outputs in
STM8S103Fx pin
description.
Remove CLK_CANCCR register from
hardware register map
DocID15441 Rev 7
Revision history
Table 19: General
characteristics.
Analog-to-digital
Table 4: Legend/abbreviations for
description.
STM8S103Kx
description.
: Standardized all reset state
Table 14: STM8S103F
devices.
Figure 37: Recommended
2
C bus and timing diagram in
Table 46: ADC accuracy with RAIN <
Table 47: ADC accuracy with RAIN <
.
list: updated
OPT2
STM8S103F.
data: updated existing
Table 6:
Table 8: General
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