STM8S103F3 STMicroelectronics, STM8S103F3 Datasheet - Page 24

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STM8S103F3

Manufacturer Part Number
STM8S103F3
Description
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S103F3

Program Memory
8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Data Memory
640 bytes true data EEPROM; endurance 300 kcycles
Ram
1 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
Pinout and pin description
5.2.3
STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description
Pin no.
Pin name
TSSOP/SO20
UFQFPN20
1
18
PD4/ BEEP/
TIM2_ CH1/
UART1 _CK
2
19
PD5/ AIN5/
UART1 _TX
3
20
PD6/ AIN6/
UART1 _RX
4
1
NRST
(2)
5
2
PA1/ OSCIN
6
3
PA2/ OSCOUT
7
4
V SS
8
5
VCAP
9
6
V DD
10
7
PA3/ TIM2_ CH3
[SPI_ NSS]
2
11
8
PB5/ I
C_ SDA
[TIM1_ BKIN]
2
12
9
PB4/ I
C_ SCL
13
10
PC3/ TIM1_CH3
[TLI] [TIM1_
CH1N]
14
11
PC4/ CLK_CCO/
TIM1_
CH4/AIN2/[TIM1_
CH2N]
15
12
PC5/ SPI_SCK
[TIM2_ CH1]
16
13
PC6/ SPI_MOSI
[TIM1_ CH1]
17
14
PC7/ SPI_MISO
[TIM1_ CH2]
18
15
PD1/ SWIM
19
16
PD2/AIN3/[TIM2_
CH3]
20
17
PD3/ AIN4/ TIM2_
CH2/ ADC_ ETR
24/113
STM8S103K3 STM8S103F3 STM8S103F2
Table 6: STM8S103Fx pin description
Input
Output
Type
Ext.
High sink
floating
wpu
Speed
(1)
interr.
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
I/O
X
X
X
O1
I/O
X
X
X
O1
S
S
S
I/O
X
X
X
HS
O3
I/O
X
X
O1
I/O
X
X
O1
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O4
I/O
X
X
X
HS
O3
I/O
X
X
X
HS
O3
DocID15441 Rev 7
Main
Default
Alternate function
function
alternate
after remap [option
(after
OD
PP
function
bit]
reset)
X
X
Port D4
Timer 2 -
channel
1/BEEP output/
UART1 clock
X
X
Port D5
Analog input 5/
UART1 data
transmit
X
X
Port D6
Analog input 6/
UART1 data
receive
Reset
X
X
Port A1
Resonator/
crystal in
X
X
Port A2
Resonator/
crystal out
Digital ground
1.8 V regulator capacitor
Digital power supply
X
X
Port A3
Timer 2
SPI master/ slave
channel 3
select [AFR1]
2
T
Port B5
I
C data
Timer 1 - break
(3)
input [AFR4]
2
T
Port B4
I
C clock
ADC external
(3)
trigger [AFR4]
X
X
Port C3
Timer 1 -
Top level interrupt
channel 3
[AFR3] Timer 1 -
inverted channel 1
[AFR7]
X
X
Port C4
Configurable
Timer 1 - inverted
clock
channel 2 [AFR7]
output/Timer 1
- channel
4/Analog input
2
X
X
Port C5
SPI clock
Timer 2 - channel 1
[AFR0]
X
X
Port C6
SPI master
Timer 1 - channel 1
out/slave in
[AFR0]
X
X
Port C7
SPI master in/
Timer 1 - channel 2
slave out
[AFR0]
X
X
Port D1
SWIM data
interface
X
X
Port D2
Analog input 3
Timer 2 - channel 3
[AFR1]
X
X
Port D3
Analog input 4/
Timer 2 -
channel 2/ADC
external trigger

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