ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet

Page 1

... LT timer w/ Wdg, AT timer w/ 1 PWM, 10-bit ADC 2 3 MHz CPU MHz RC -40 °C to +125 °C SO8 150”, DIP8, DFN8, DIP16 Rev 2 ST7LITEU05 ST7LITEU09 ADC, timers SO8 150” DFN8 DD ST7LITEU09 2K 128 = 8 MHz CPU (1) 1/139 www.st.com 1 ...

Page 2

... Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.1 5.4.2 5.4.3 5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/139 In-circuit programming (ICP Application Programming (IAP Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash control/status register (FCSR Read operation (E2LAT= Write operation (E2LAT= Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ST7LITEU05 ST7LITEU09 ...

Page 3

... ST7LITEU05 ST7LITEU09 5.7.1 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 Reset sequence manager (RSM 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5.1 7.5.2 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Priority management Interrupts and low power mode 8.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 ...

Page 4

... External interrupt control register 1 (EICR1 External interrupt control register 2 (EICR2 Low voltage detector (LVD Auxiliary voltage detector (AVD Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ST7LITEU05 ST7LITEU09 ...

Page 5

... ST7LITEU05 ST7LITEU09 11.1.4 11.1.5 11.1.6 11.1.7 11.2 12-bit autoreload timer (AT 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 10-bit A/D converter (ADC 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.1.6 12.1.7 12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.1 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.1 13.1.2 13.1.3 13.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction ...

Page 6

... Functional EMS (electro magnetic susceptibility 107 EMI (electromagnetic interference 108 Absolute maximum ratings (electrical sensitivity 108 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Option byte 127 Option byte 128 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ST7LITEU05 ST7LITEU09 ...

Page 7

... ST7LITEU05 ST7LITEU09 15.3.4 15.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Order codes for development and programming tools . . . . . . . . . . . . . 132 Contents 7/139 ...

Page 8

... Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 89 Table 41. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 90 Table 42. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 43. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 44. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 45. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 46. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 47. Thermal characteristics Table 48. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8/139 ST7LITEU05 ST7LITEU09 ...

Page 9

... ST7LITEU05 ST7LITEU09 Table 49. Operating characteristics with LVD Table 50. Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 51. Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 99 Table 52. Internal RC oscillator characteristics (5.0 V calibration Table 53. Internal RC oscillator characteristics (3.3 V calibration 100 Table 54. Supply current characteristics 101 Table 56. ...

Page 10

... Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature 100 Figure 46. Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 103 Figure 47. Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 103 Figure 48. Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int 10/139 ST7LITEU05 ST7LITEU09 supply voltage . . . . . . . . . . . . . . . . . . . 97 DD ...

Page 11

... ST7LITEU05 ST7LITEU09 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 49. Idd vs temp @VDD 5 V & int MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 50. Idd vs temp @VDD 5 V & int MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 51. Idd vs temp @VDD 5V & int MHz 104 Figure 52. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 53 ...

Page 12

... Section 13 on page Internal AWU RC osc. Clock 8-MHz RC osc. Lite timer with watchdog LVD Power Port A supply 12-bit auto- reload timer Control 8-bit core ALU 10-bit ADC 2 Kbyte Flash memory Data EEPROM (128 Bytes) RAM (128 Bytes) ST7LITEU05 ST7LITEU09 95. PA5:0 (6 bits) ...

Page 13

... ST7LITEU05 ST7LITEU09 2 Pin description Figure 2. 8-pin SO and DIP package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 / MCO High sink capability 2. eix : associated external interrupt vector Figure 3. 8-pin DFN package pinout PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 / MCO High sink capability 2. eix : associated external interrupt vector ...

Page 14

... MUXCR2) will have no effect on PA3 functionality. Refer to “Register description” on page 41. 14/139 1) 2) Reserved RESET 3 PA0 (HS) / AIN0 / ATPWM 1 ei0 ICCCLK 4 1 PA1 (HS) / AIN1 ei1 12 5 ei4 NC 6 ei3 11 ICCDATA 7 10 PA2 (HS) / LTIC / AIN2 PA3 ei2 ST7LITEU05 ST7LITEU09 ...

Page 15

... ST7LITEU05 ST7LITEU09 Legend / Abbreviations for Type input output supply In/Output level: C Output level High sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ● Output open drain push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state ...

Page 16

... Short addressing Table ) RAM (zero page) 00C0h RAM 64-Byte Stack 00FFh Data PROGRAM MEMORY F800h FBFFh (2K) FC00h FFFFh 10) 32. ST7LITEU05 ST7LITEU09 5) mapped in the upper part of the ST7 1) DEE0h RCCRH0 DEE1h RCCRL0 DEE2h RCCRH1 DEE3h RCCRL1 2K FLASH 1 Kbyte SECTOR 1 1 Kbyte SECTOR 0 ...

Page 17

... ST7LITEU05 ST7LITEU09 Table 3. Hardware register map Address Block Register label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h to 000Ah 000Bh Lite LTCSR 000Ch timer LTICR 000Dh ATCSR 000Eh CNTRH 000Fh CNTRL Auto-reload 0010h ATRH timer 0011h ATRL 0012h PWMCR 0013h PWM0CSR ...

Page 18

... For a description of the DM registers, see the ST7 ICC Protocol Reference Manual. 18/139 Register name AWU prescaler register AWU control/status register DM control register DM status register DM breakpoint register 1 high DM breakpoint register 1 low DM breakpoint register 2 high DM breakpoint register 2 low Reserved area (47 bytes) ST7LITEU05 ST7LITEU09 Reset Remarks (1) (1) status FFh R/W 00h R/W 00h R/W ...

Page 19

... ST7LITEU05 ST7LITEU09 4 Flash program memory 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on- board using In-Circuit Programming or In-Application Programming ...

Page 20

... K, no additional components are needed. In all cases the user must 20/139 PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 3.3k (See Note 5) See Note 1 and Caution See Note 1 ST7 ST7LITEU05 ST7LITEU09 APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 APPLICATION I/O ...

Page 21

... ST7LITEU05 ST7LITEU09 ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). ...

Page 22

... When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. Reset value: 000 0000 (00h Address Register 7 label (Hex.) FCSR - 002Fh 0 Reset Value 22/139 Read/write ST7LITEU05 ST7LITEU09 . 0 OPT LAT PGM OPT LAT PGM ...

Page 23

... ST7LITEU05 ST7LITEU09 5 Data EEPROM 5.1 Introduction The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 Main features ● bytes programmed in the same cycle ● ...

Page 24

... Data EEPROM programming flowchart 24/139 Figure 10. READ MODE E2LAT=0 E2PGM=0 WRITE BYTES READ BYTES IN EEPROM AREA IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE E2PGM=1 (set by software) 0 CLEARED BY HARDWARE ST7LITEU05 ST7LITEU09 WRITE MODE E2LAT=1 E2PGM=0 E2LAT=1 1 E2LAT ...

Page 25

... ST7LITEU05 ST7LITEU09 Figure 9. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit Set by USER application E2PGM bit programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 Power saving modes 5.4.1 Wait mode The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode ...

Page 26

... Programming finished or not yet started 1: Programming cycle is in progress Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed. 26/139 Read operation not possible ERASE CYCLE WRITE CYCLE t PROG Read/write ST7LITEU05 ST7LITEU09 Read operation possible LAT PGM 0 0 E2LAT E2PGM ...

Page 27

... ST7LITEU05 ST7LITEU09 Table 4. Data EEPROM register map and reset values Address Register Label (Hex.) EECSR 0030h Reset Value Data EEPROM E2LAT E2PGM 27/139 ...

Page 28

... The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (Program Counter High which is the MSB). 28/139 Figure 11 are not present in the memory mapping and are ST7LITEU05 ST7LITEU09 ...

Page 29

... ST7LITEU05 ST7LITEU09 Figure 11. CPU registers 15 PCH RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE = 1 15 RESET VALUE = STACK HIGHER ADDRESS undefined value 6.3.4 Condition code register (CC) The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions ...

Page 30

... Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. 30/139 Read/write SP5 SP4 SP3 Read/write Figure 12). ST7LITEU05 ST7LITEU09 th bit of the result SP2 SP1 SP0 ...

Page 31

... ST7LITEU05 ST7LITEU09 The least significant byte of the Stack Pointer (called S) can be directly accessed instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost ...

Page 32

... It must be calibrated to obtain the frequency Conditions ST7LITEU05/ST7LITEU09 address ° MHz 3 ° MHz RC ST7LITEU05 ST7LITEU09 supply voltages at 25 °C, DD (1) DEE0h (CR[9:2] bits) (1) DEE1h (CR[1:0] bits) (1) DEE2h (CR[9:2] bits) (1) DEE3h (CR[1:0] bits) ...

Page 33

... ST7LITEU05 ST7LITEU09 Note: In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in See “Electrical characteristics” on page 95. for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100nF, between the V device ...

Page 34

... CK0 33kHz AWU RC /2 DIVIDER f CLKIN 13-BIT LITE TIMER COUNTER f OSC 0 f /32 /32 DIVIDER 1 OSC MCO SMS ST7LITEU05 ST7LITEU09 AWU RC Internal RC RCCR SICSR CKCNTCSR RC/AWU Clock Controller AWU CK Ext Clock AVDTHCR CKSEL[1:0] Option bits f LTIMER (1ms timebase @ 8 MHz f OSC f CPU TO CPU AND ...

Page 35

... ST7LITEU05 ST7LITEU09 7.3 Register description 7.3.1 Main clock control/status register (MCCSR) Reset value: 0000 0000 (00h Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable bit This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. ...

Page 36

... CR0 0 0 Read/write Section 8.4: System integrity management (SI) on CK0 0 0 Read/write Figure 14 on page 34 CK1 CK0 others Section 8.4: System integrity management ST7LITEU05 ST7LITEU09 0 LVDRF AVDF AVDIE 32 AVD1 AVD0 and the following f OSC f RC/2 f RC/4 f RC/8 f RC/ ...

Page 37

... ST7LITEU05 ST7LITEU09 7.3.5 Clock controller control/status register (CKCNTCSR) Reset Value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware switch from AWU to RC requested 1: AWU clock activated and temporization completed Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware ...

Page 38

... Table 8. CPU clock cycle delay External clock (connected to CLKIN pin) Figure 15. Reset sequence phases 38/139 Clock source Internal RC oscillator AWURC RESET INTERNAL RESET Active Phase 256 OR 512 CLOCK CYCLES ST7LITEU05 ST7LITEU09 Figure 16: Figure 15: CPU clock cycle delay 512 256 FETCH VECTOR ...

Page 39

... ST7LITEU05 ST7LITEU09 Figure 16. Reset block diagram RESET 1. See “Illegal opcode reset” on page 92. for more details on illegal opcode reset conditions. 7.4.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device ...

Page 40

... V IT-(LVD) EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 40/139 . w(RSTL)out V DD LVD EXTERNAL RESET RUN RUN ACTIVE ACTIVE PHASE PHASE t h(RSTL)in WATCHDOG UNDERFLOW ST7LITEU05 ST7LITEU09 WATCHDOG RESET RESET RUN RUN ACTIVE PHASE t w(RSTL)out INTERNAL RESET (256 or 512 T ) CPU VECTOR FETCH ...

Page 41

... ST7LITEU05 ST7LITEU09 7.5 Register description 7.5.1 Multiplexed IO reset control register 1 (MUXCR1) Reset value: 0000 0000 (00h) 7 MIR15 MIR14 7.5.2 Multiplexed IO reset control register 0 (MUXCR0) Reset value: 0000 0000 (00h) 7 MIR7 MIR6 Bits 15:0 = MIR[15:0] This 16-bit register is read/write by software but can be written only once between two reset events cleared by hardware after a reset ...

Page 42

... Halt low power mode (refer to the “Exit from Halt” column in the Interrupt Mapping table). 8.1 Non maskable software interrupt This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit serviced according to the flowchart in 42/139 ST7LITEU05 ST7LITEU09 Figure 18. Figure 18. ...

Page 43

... ST7LITEU05 ST7LITEU09 8.2 External interrupts External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available) ...

Page 44

... External interrupt 4 AVD interrupt AT TIMER output compare PWMxCSR interrupt or ATCSR AT TIMER overflow Interrupt ATCSR LITE TIMER input capture LTCSR interrupt LITE TIMER RTC1 interrupt LTCSR Not used Not used ST7LITEU05 ST7LITEU09 Exit Priority from label order Halt yes FFFEh-FFFFh N/A no FFFCh-FFFDh (1) yes FFFAh-FFFBh ...

Page 45

... ST7LITEU05 ST7LITEU09 8.3.1 External interrupt control register 1 (EICR1) Reset value: 0000 0000 (00h Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 (Port C) according to Bits 3:2 = IS1[1:0] ei1 sensitivity bits These bits define the interrupt sensitivity for ei1 (Port B) according to ...

Page 46

... During a low voltage detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. 46/139 for further details. reference value. This means that it secures the power-up as well IT-(LVD) is rising DD is falling DD Figure 19. 127. value (guaranteed for the oscillator frequency) is above V DD ST7LITEU05 ST7LITEU09 DD reference value IT+(LVD) is below: DD supply , IT-(LVD) ...

Page 47

... ST7LITEU05 ST7LITEU09 Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application recommended to pull V conditions. Refer to circuit example in The LVD is an optional function which can be selected by option byte. See page 127. It allows the device to be used without any external Reset circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset ...

Page 48

... DD threshold (AVDF bit is set). Section 13.3.2 on page 98 DD Early warning interrupt (Power has dropped, MCU not not yet in reset) V hyst 0 1 RESET INTERRUPT Cleared by reset Description ST7LITEU05 ST7LITEU09 Figure 21. warning state DD and Section 13.3.3 on page INTERRUPT Cleared by hardware for ...

Page 49

... ST7LITEU05 ST7LITEU09 Table 13. Description of interrupt events Interrupt event AVD event 8.4.4 Register description System integrity (SI) control/status register (SICSR) Reset value: 0000 0x00 (0xh CR1 Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy ...

Page 50

... SICSR 003Ah Reset value AVDTHCR 003Eh Reset value 50/139 CK0 0 Read/write 32 CK2 CK1 CK0 ST7LITEU05 ST7LITEU09 0 0 AVD1 Functionality Low Medium High AVD off LVDRF AVDF AVD1 AVD0 0 AVDIE 0 ...

Page 51

... ST7LITEU05 ST7LITEU09 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ● Active-halt ● Auto-wakeup from Halt (AWUFH) ● Halt After a Reset the normal operating mode is selected by default (RUN mode). This mode ...

Page 52

... NORMAL RUN MODE 24. OSCILLATOR PERIPHERALS WFI INSTRUCTION CPU I BIT N N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT 256 OR 512 CPU CLOCK CYCLE OSCILLATOR PERIPHERALS CPU I BIT FETCH RESET VECTOR OR SERVICE INTERRUPT ST7LITEU05 ST7LITEU09 /32 f OSC REQUEST ON ON OFF 0 RESET Y ON OFF ON 0 DELAY ...

Page 53

... ST7LITEU05 ST7LITEU09 9.4 Active-halt and Halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active- Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: Table 16 ...

Page 54

... INTERRUPT OSCILLATOR Y PERIPHERALS CPU I BIT 256 OR 512 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BITS FETCH RESET VECTOR OR SERVICE INTERRUPT 44 Reset. When exiting Halt mode by means of a Reset or ST7LITEU05 ST7LITEU09 ON 2) OFF OFF OFF Table 10: Figure 28) ...

Page 55

... ST7LITEU05 ST7LITEU09 Figure 27. Halt timing overview Figure 28. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 10, “ ...

Page 56

... Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run 56/139 AWU RC oscillator to 8-bit Timer input capture f AWU_RC AWUFH interrupt AWUFH /64 divider prescaler/1 .. 255 (ei0 source) and then calculating the right prescaler value. AWU_RC ST7LITEU05 ST7LITEU09 ). Its frequency is divided by AWU_RC ...

Page 57

... ST7LITEU05 ST7LITEU09 mode. This connects measured using the main oscillator clock as a reference timebase. AWU_RC Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: ● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see ● ...

Page 58

... AWU RC OSC Y MAIN OSC PERIPHERALS CPU I[1:0] BITS 256 OR 512 CPU CLOCK CYCLE DELAY AWU RC OSC MAIN OSC PERIPHERALS CPU I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Read/Write ST7LITEU05 ST7LITEU09 ON OFF OFF OFF 10 OFF ON OFF OFF AWUF AWUM ...

Page 59

... ST7LITEU05 ST7LITEU09 Bit 2 = AWUF Auto Wake Up flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value AWU interrupt occurred 1: AWU interrupt occurred Bit 1 = AWUM Auto Wake Up Measurement bit This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite timer ...

Page 60

... AWU register map and reset values Address Register 7 (Hex.) label AWUPR AWUPR7 0049h Reset 1 value AWUCSR 004Ah Reset 0 value 60/139 1 -------------------- + t RCSTRT f AWURC AWUPR6 AWUPR5 AWUPR4 ST7LITEU05 ST7LITEU09 AWUPR3 AWUPR2 AWUPR1 AWUF AWUM 0 AWUPR0 1 AWUEN ...

Page 61

... ST7LITEU05 ST7LITEU09 10 I/O ports 10.1 Introduction The I/O port offers different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O port contains pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output ...

Page 62

... The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. 62/139 ST7LITEU05 ST7LITEU09 ...

Page 63

... ST7LITEU05 ST7LITEU09 Table 19. DR value and output pin status Note: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 10.2.3 Alternate functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected ...

Page 64

... ALTERNATE 1 OUTPUT 0 ALTERNATE ENABLE If implemented 1 0 FROM OTHER BITS POLARITY SELECTION (1) Pull-up Off On Off ST7LITEU05 ST7LITEU09 P-BUFFER V DD (see table below) PULL-UP (see table below PULL-UP PAD CONDITION N-BUFFER DIODES (see table below) ANALOG INPUT CMOS SCHMITT TRIGGER ALTERNATE ...

Page 65

... ST7LITEU05 ST7LITEU09 Table 21. I/O port configurations PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content ...

Page 66

... Figure 33. Interrupt I/O port state transitions 66/139 Description Enable Event control flag bit DDRx - ORx INPUT INPUT OUTPUT floating/pull-up floating open-drain interrupt (reset state DDR, OR ST7LITEU05 ST7LITEU09 Section 13.8 on page Exit Exit from from Wait Halt Yes Yes Figure 33. 11 OUTPUT push-pull ...

Page 67

... ST7LITEU05 ST7LITEU09 The I/O port register configurations are summarised in the following table: Table 24. Port configuration Port Pin name PA0:2, PA4:5 (1) Port A PA3 1. IS4[1: the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes. Refer to EICR2 description on 2. After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers ...

Page 68

... Watchdog – Enabled by hardware or software (configurable by option byte) – Optional reset on HALT instruction (configurable by option byte) – Automatically resets the device unless disable bit is refreshed – Software reset (forced watchdog reset) – Watchdog reset status flag 68/139 ST7LITEU05 ST7LITEU09 ) OSC ...

Page 69

... ST7LITEU05 ST7LITEU09 Figure 34. Lite timer block diagram f OSC 13-bit UPCOUNTER LTICR LTIC INPUT CAPTURE REGISTER 11.1.3 Functional description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from 1F39h to 00h counter overflow events ...

Page 70

... ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 70/139 HARDWARE CLEARS WDGD BIT t WDG (2ms @ 8 MHz f ) OSC SOFTWARE SETS WDGD BIT ST7LITEU05 ST7LITEU09 WATCHDOG RESET ...

Page 71

... ST7LITEU05 ST7LITEU09 11.1.5 Low power modes Table 26. Description of low power modes Mode Wait Active-Halt Halt 11.1.6 Interrupts Table 27. Interrupt events Event Interrupt event flag Timebase Event TBF IC Event ICF Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). ...

Page 72

... LVD reset occurs. It can be cleared by software after a read access to the LTCSR register watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). 72/139 TB TBIE TBF Read / Write * 8000 ( MHz) OSC * 16000 ( MHz) OSC ST7LITEU05 ST7LITEU09 0 WDGR WDGE WDGD ...

Page 73

... ST7LITEU05 ST7LITEU09 Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 = WDGD Watchdog Reset Delay This bit is set by software cleared by hardware at the end of each t 0: Watchdog reset not delayed 1: Watchdog reset delayed Lite Timer Input Capture register (LTICR) ...

Page 74

... CK1 CK0 OVF f COUNTER 12-BIT UPCOUNTER CNTR 12-BIT AUTORELOAD VALUE ATR CMPF0 bit OE0 bit 0 COMP- PARE 1 ST7LITEU05 ST7LITEU09 ) OVF INTERRUPT REQUEST 0 OVFIE CMPIE CMP INTERRUPT REQUEST CMPF0 Update on OVF Event OE0 bit OP0 bit POL- f PWM ARITY on page 80). ...

Page 75

... ST7LITEU05 ST7LITEU09 PWM frequency and duty cycle The PWM signal frequency (f value PWM COUNTER Following the above formula register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case ...

Page 76

... OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal. The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written. 76/139 ATR= FFDh FFDh FFEh FFFh FFDh FFEh ST7LITEU05 ST7LITEU09 FFFh FFDh FFEh t ...

Page 77

... ST7LITEU05 ST7LITEU09 11.2.4 Low power modes Table 29. Description of low power modes Mode Slow Wait Active-halt Halt 11.2.5 Interrupts Table 30. Interrupt events (1) Interrupt event Overflow Event CMP Event 1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction) ...

Page 78

... When a counter overflow occurs, the counter restarts from the value specified in the ATR register. 78/139 COUNTER 0 0 Read only CN5 CN4 Read only = f , special care must be taken when CNTRL values close to FFh timer CPU ST7LITEU05 ST7LITEU09 cycle (up to 1ms depending on the clock CN11 CN10 CN9 CN3 CN2 CN1 8 CN8 0 CN0 ...

Page 79

... ST7LITEU05 ST7LITEU09 Auto reload register (ATRH) Reset value: 0000 0000 (00h Auto reload register (ATRL) Reset value: 0000 0000 (00h) 7 ATR7 ATR6 Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs ...

Page 80

... Read/Write Read/Write CK1 CN7 CN6 CN5 CN4 ST7LITEU05 ST7LITEU09 0 0 OP0 CMPF0 OE0 CK0 OVF OVFIE CMPIE CN11 CN10 CN9 CN8 CN3 CN2 ...

Page 81

... ST7LITEU05 ST7LITEU09 Table 32. Register map and reset values (continued) Address Register label (Hex.) ATRL 11 Reset Value PWMCR 12 Reset Value PWM0CSR 13 Reset Value DCR0H 17 Reset Value DCR0L 18 Reset Value 11.3 10-bit A/D converter (ADC) 11.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry ...

Page 82

... ADCDRL ) is greater than V (high-level voltage reference) then the AIN lower than V (low-level voltage reference) then the conversion AIN SS ] SAMPLE input voltage to be measured is loaded into the C AIN ] HOLD ST7LITEU05 ST7LITEU09 f ADC ADCCSR CH0 ANALOG TO DIGITAL CONVERTER C ADC ...

Page 83

... ST7LITEU05 ST7LITEU09 cycles) and the C the optimum analog to digital conversion accuracy. The total conversion time CONV = SAMPLE While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement ...

Page 84

... These bits are set and cleared by software. They select the analog input to convert. 84/139 No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time t (see Electrical Characteristics) before accurate conversions can be STAB performed. ADON 0 Read/Write (Except bit 7 read only) ST7LITEU05 ST7LITEU09 Description 0 CH2 CH1 0 CH0 ...

Page 85

... ST7LITEU05 ST7LITEU09 Table 34. Channel selection Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the EOC bit and starts a new conversion. ADC data register high (ADCDRH) Reset value: 0000 0000 (00h ADC Control/data register Low (ADCDRL) ...

Page 86

... ADCDRH 0035h Reset value ADCDRL 0036h Reset value 86/139 EOC SPEED ADON ST7LITEU05 ST7LITEU09 CH2 CH1 CH0 SLOW ...

Page 87

... ST7LITEU05 ST7LITEU09 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Table 37. Description of addressing modes Addressing mode The ST7 instruction set is designed to minimize the number of bytes required per instruction so, most of the addressing modes may be subdivided in two submodes called long and short: ● ...

Page 88

... Interrupt subroutine return Set interrupt mask Reset interrupt mask Set carry flag Reset carry flag Reset stack pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero complement Byte multiplication ST7LITEU05 ST7LITEU09 Pointer Pointer Length address size (Bytes) 00..FF word + ...

Page 89

... ST7LITEU05 ST7LITEU09 Table 39. Instructions supporting inherent addressing mode (continued) Inherent instruction SLL, SRL, SRA, RLC, RRC SWAP 12.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Table 40. Instructions supporting inherent immediate addressing mode ...

Page 90

... Table 41. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Long and short instructions AND, OR, XOR ADC, ADD, SUB, SBC 90/139 Instructions LD CP BCP ST7LITEU05 ST7LITEU09 Function Load Compare Logical operations Arithmetic addition/subtraction operations Bit compare ...

Page 91

... ST7LITEU05 ST7LITEU09 Table 41. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued) Short instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative modes (direct, indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Table 42. ...

Page 92

... AND OR XOR CPL BSET BRES BTJT BTJF ADC ADD SUB SBC SLL SRL SRA RLC JRA JRT JRF JP JRxx TRAP WFI HALT IRET SIM RIM SCF RCF ST7LITEU05 ST7LITEU09 NEG MUL RRC SWAP SLA CALL CALLR NOP RET ...

Page 93

... ST7LITEU05 ST7LITEU09 Table 44. Illegal opcode detection Mnemo Description ADC Add with carry ADD Addition AND Logical and BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative ...

Page 94

... <= Dst <= 0 reg <= Dst <= 0 reg => Dst => C reg, M Dst7 => Dst => C reg Dst[7..4]<=>Dst[3..0] reg, M tnz lbl1 S/W interrupt XOR M A ST7LITEU05 ST7LITEU09 Src reg ...

Page 95

... ST7LITEU05 ST7LITEU09 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at T selected temperature range) ...

Page 96

... V could damage the device if an unexpected change of the I/O configuration DD SS < Ratings (1) power lines (source) DD (1) ground lines (sink) SS (4) ST7LITEU05 ST7LITEU09 ST7 PIN Maximum value 7 see Section 13.7.3 on page 108 maximum cannot be IN Maximum value 75 150 20 40 -25 ± ...

Page 97

... ST7LITEU05 ST7LITEU09 2. I must never be exceeded. This is implicitly insured if V INJ(PIN) current must be limited externally to the I V < Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0 ...

Page 98

... LVD may not release properly the reset of the MCU DD down ensure optimum restart conditions. Refer to circuit example in DD Parameter Conditions High threshold Med. threshold (V rise) DD Low threshold High threshold Med. threshold (V fall) DD Low threshold V IT+ ST7LITEU05 ST7LITEU09 Min Typ 3.9 4.2 3.2 3.5 2.5 2.7 3.7 4.0 3.0 3.3 2.4 2.6 -V 150 IT- (LVD) 20 ...

Page 99

... ST7LITEU05 ST7LITEU09 Table 51. Voltage drop between AVD flag set and LVD reset generation Parameter AVD med. threshold - AVD low. threshold AVD high. threshold - AVD low threshold AVD high. threshold - AVD med. threshold AVD low threshold - LVD low threshold AVD med. threshold - LVD low threshold AVD med ...

Page 100

... -40 ° ° 3 ° 3 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 ST7LITEU05 ST7LITEU09 Min Typ Max Unit 4.3 8 -1.0 +1.0 (2) -2.5 +4.0 (2) -3.0 +5.0 -4.0 +2.5 ( 2.4-6.0 V and temperature DD RC5V@-45C RC5V@25C RC5V@90C RC5V@130C RC5V@0C = 2.4-6.0V and temperature DD RC3.3V@-45C RC3.3V@25C RC3.3V@90C RC3.3V@130C RC3.3V@0C MHz % % % % s ...

Page 101

... ST7LITEU05 ST7LITEU09 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped) ...

Page 102

... (no load), all peripherals in reset state; CPU clock provided divided by 32. All I/O pins in input mode with a static value at V OSC based on f divided by 32. All I/O pins in input mode with a static value at V OSC ST7LITEU05 ST7LITEU09 (1) Min Typ Max Unit 3.2 5.5 5.7 8.5 ...

Page 103

... ST7LITEU05 ST7LITEU09 Figure 46. Typical I Figure 47. Typical I Figure 48. Typical MHz in run mode vs. internal clock frequency and V DD Idd RUN mode @amb vs int clock freq 6. 5. 4.00 3.00 2.00 1.00 0.00 VDD [V] in WFI mode vs. internal clock frequency and V DD Idd WFI mode @amb vs int RC freq 2 ...

Page 104

... Figure 49. Idd vs temp @V Figure 50. Idd vs temp @V Figure 51. Idd vs temp @V 104/139 5 V & int MHz DD 6.0 5.0 4.0 3.0 2.0 1.0 0.0 Temp [° & int MHz DD 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Temp [°C] 5V & int MHz DD 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Temp [°C] ST7LITEU05 ST7LITEU09 run wfi slow slowwait acthlt run wfi run wfi ...

Page 105

... ST7LITEU05 ST7LITEU09 13.4.3 On-chip peripherals Table 56. On-chip peripheral characteristics Symbol Parameter I 12-bit auto-reload timer supply current DD(AT) I ADC supply current when converting DD(ADC) 1. Not tested in production, guaranteed by characterization. 2. Data based on a differential I measurement between reset configuration (timer stopped) and the timer running in PWM ...

Page 106

... Power down mode / HALT decreases. A Conditions Refer to operating range of V with T Section 13.3.1: General A, operating conditions on page +125 °C A (1) ( +55 ° +25 °C A decreases. A ST7LITEU05 ST7LITEU09 Min Typ Max 1.6 Min Typ Max 2.4 5 0.32 0.64 (3) 20 10k 2.6 100 0 0.1 Min Typ Max DD 2 ...

Page 107

... ST7LITEU05 ST7LITEU09 13.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ● ...

Page 108

... IEC 1000-4-4 Conditions 0.1 MHz to 30 MHz +25 ° SO8 package, 30 MHz to 130 MHz conforming to SAE J 130 MHz to 1 GHz 1752/3 SAE EMI Level ST7LITEU05 ST7LITEU09 Conditions +25 ° MHz OSC +25 ° MHz OSC Max vs ...

Page 109

... ST7LITEU05 ST7LITEU09 Table 64. ESD absolute maximum ratings Symbol Electro-static discharge voltage V ESD(HBM) Electro-static discharge voltage V ESD(CDM) 1. Data based on characterization results, not tested in production. Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance. ● A supply overvoltage is applied to each power supply pin ● ...

Page 110

... Static peak current value taken at a fixed V ST7XXX 10k UNUSED I/O PORT vs. V with -45°C 50 25°C 90°C 130° Vdd [V] ST7LITEU05 ST7LITEU09 Min Typ Max current characteristics described in PU UNUSED I/O PORT 10k ST7XXX Unit CPU value, and ...

Page 111

... ST7LITEU05 ST7LITEU09 Figure 54. Typical R 13.8.2 Output driving current Subject to general operating conditions for V Table 67. Output driving current characteristics Symbol Parameter Output low level voltage for PA3/RESET standard I/O pin (see ( Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time ...

Page 112

... Iol [mA (standard pins 1200 -45°C 1000 25°C 800 90°C 130°C 600 400 200 Iol [mA] ST7LITEU05 ST7LITEU09 Table 46 on page 96 and the sum (I/O ports ...

Page 113

... ST7LITEU05 ST7LITEU09 Figure 58. Typical V Figure 59. Typical V Figure 60. Typical 2.4 V (HS pins 1200 -45°C 1000 25°C 90°C 800 130°C 600 400 200 Iol [mA (HS pins 1400 -45°C 1200 25°C 1000 90°C 800 130°C ...

Page 114

... Iol [mA (HS pins 1000 -45°C 900 25°C 800 90°C 130°C 700 600 500 400 300 200 100 Iol [mA] ST7LITEU05 ST7LITEU09 ...

Page 115

... ST7LITEU05 ST7LITEU09 Figure 64. Typical V 100 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Figure 65. Typical V 200 180 160 140 120 100 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 vs. V (HS pins 500 450 -45°C 400 25°C 90°C 350 130°C 300 250 200 150 100 2.4 2.6 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 Vdd [V] 900 800 700 600 ...

Page 116

... To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below t 116/139 Conditions ( Internal reset sources (4) . VSS can be ignored. h(RSTL)in ST7LITEU05 ST7LITEU09 Min Typ V 0.3xV SS - 0.3 0.7xV ( ( 200 Table 46 on page 96 ...

Page 117

... ST7LITEU05 ST7LITEU09 Figure 66. RESET pin protection when LVD is enabled Required EXTERNAL RESET 0. Please refer to Section 12.2.1: Illegal opcode reset on page 92 conditions The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog) ...

Page 118

... MHz ADC MHz, CPU MHz ADC =25 °C and 2 2.7 V operating range is 1 MHz. DD ST7LITEU05 ST7LITEU09 INTERNAL RESET WATCHDOG PULSE GENERATOR ILLEGAL OPCODE 116. Otherwise the reset will not be , and T unless otherwise specified. A (1) Min Typ Max ...

Page 119

... ST7LITEU05 ST7LITEU09 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum value). Data guaranteed by Design, not tested in production. 4. The stabilization time of the A/D converter is masked by the first t valid. Figure 68. Typical application with ADC V AIN Table 70 ...

Page 120

... MHz, CPU f =1 MHz ADC Digital Result ADCDR V V – 1LSB = ------------------------------- - IDEAL 1024 ( LSB IDEAL ST7LITEU05 ST7LITEU09 Typ Max 2.5 3.5 1.1 1.5 0.5 1.5 (1) 1.1 2.5 1.2 2 (3) (1) D 1021 1022 1023 1024 V (LSB ) in IDEAL V DD Unit LSB ...

Page 121

... ST7LITEU05 ST7LITEU09 14 Package characteristics In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK® ...

Page 122

... Min Typ Max 0.80 0.90 1.00 0.00 0.02 0.05 0.20 0.25 0.30 0.35 4.50 3.50 3.65 3.75 3.50 1.96 2.11 2.21 0.80 0.30 0.40 0.50 Number of pins ST7LITEU05 ST7LITEU09 (1) inches Min Typ 0.0315 0.0354 0.0008 0.0079 0.0098 0.0118 0.1772 0.1378 0.1437 0.1378 0.0772 0.0831 0.0315 0.0118 0.0157 45° Max 0.0394 0.0020 0.0138 0.1476 0.0870 0.0197 ...

Page 123

... ST7LITEU05 ST7LITEU09 Table 74. 8-pin plastic small outline package - 150-mil width, mechanical data Dim Values in inches are converted from mm and rounded to 4 decimal digits. Figure 72. 8-pin plastic dual in-line outline package - 300-mil width, package outline mm Min ...

Page 124

... Values in inches are converted from mm and rounded to 4 decimal digits. 124/139 millimeters Typ Min Max 5.33 0.38 3.3 2.92 4.95 0.46 0.36 0.56 1.52 1.14 1.78 0.25 0.2 0.36 9.27 9.02 10.16 7.87 7.62 8.26 6.35 6.1 7. 10.92 3.3 2.92 3.81 ST7LITEU05 ST7LITEU09 (1) inches Typ Min Max 0.2098 0.0150 0.1299 0.1150 0.1949 0.0181 0.0142 0.0220 0.0598 0.0449 0.0701 0.0098 0.0079 0.0142 0.3650 0.3551 0.4000 0.3098 0.3000 0.3252 0.2500 0.2402 0.2799 0.1000 0.3000 0.4299 0.1299 0.1150 0.1500 ...

Page 125

... ST7LITEU05 ST7LITEU09 Figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline Table 76. 16-pin plastic dual in-line package, 300-mil width, mechanical data Dim Values in inches are converted from mm and rounded to 4 decimal digits. ...

Page 126

... P internal power (I DD application. 126/139 Ratings (1) ( and P is the port power dissipation depending on the ports used in the DD PORT ST7LITEU05 ST7LITEU09 Value DIP8 82 SO8 130 DFN8 (on 4-layer PCB) 50 DFN8 (on 2-layer PCB) 106 150 DIP8 300 ...

Page 127

... ST7LITEU05 and ST7LITEU09 devices : they are factory- programmed XFlash devices. ST7FLITEU05 and ST7FLITEU09 XFlash devices are XFlash versions of ST7LITEU05 and ST7LITEU09 devices. They are shipped to customers with a default program memory content (FFh). The FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option Bytes while the FASTROM devices are factory-configured ...

Page 128

... Bit 0 = FMP_W FLASH write protection This option indicates if the FLASH program memory is write protected. 0: Write protection off 1: Write protection on Warning: 128/139 SEC0 When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. ST7LITEU05 ST7LITEU09 SEC1 Section 4.5 ...

Page 129

... ST7LITEU05 ST7LITEU09 OPTION BYTE 0 7 SEC Reserved Default value 15.2 Ordering information Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh ...

Page 130

... For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 1. DIP16 for development or tool prototyping purposes only, not orderable in production quantities. 130/139 ST7LITEU05 ST7LITEU09 ST7 F LITEU05 ...

Page 131

... Device configuration and ordering information ST7LITEU0 FASTROM microcontroller option list (Last update: October 2008 Tube [ ] Tape & Reel [ ] Tube [ ] Tape & Reel [ ] Tray (ST7LITEU09 only Yes " " -40°C to +85° -40°C to +125° External clock [ ] AWU RC oscillator [ ] Internal RC oscillator [ ] 0 ...

Page 132

... Order codes for development and programming tools Table 81 below lists the ordering codes for the ST7LITEU0x development and programming tools. For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. 132/139 ST7LITEU05 ST7LITEU09 ...

Page 133

... ST7LITEU05 ST7LITEU09 Table 81. Development tool order codes for the ST7LITEU0x family In-circuit debugger, RLink series Supported Starter kit products without demo board ST7FLITEU05 (2) STX-RLINK ST7FLITEU09 1. Available from ST or from Raisonance, www.raisonance.com 2. USB connection Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” product and tool selection guide for connection kit ordering information 4 ...

Page 134

... PWM Management for BLDC Motor Drives Using the ST72141 AN1130 An Introduction to Sensorless Brushless DC Motor Drive Applications with the ST72141 AN1148 Using the ST7263 for Designing a USB Mouse AN1149 Handling Suspend Mode on a USB Mouse AN1180 Using the ST7263 Kit to Implement a USB Game Pad 134/139 ST7LITEU05 ST7LITEU09 Description ...

Page 135

... ST7LITEU05 ST7LITEU09 Table 82. ST7 application notes (continued) Identification AN1276 BLDC Motor Start Routine for the ST72141 Microcontroller AN1321 Using the ST72141 Motor Control MCU in Sensor Mode AN1325 Using the ST7 USB LOW-SPEED Firmware V4.x AN1445 Emulated 16-bit Slave SPI AN1475 Developing an ST7265X Mass Storage Application ...

Page 136

... Device Firmware Upgrade (DFU) Implementation for ST7 USB Applications AN1601 Software Implementation for ST7DALI-EVAL AN1603 Using the ST7 USB Device Firmware Upgrade Development Kit (DFU-DK) AN1635 ST7 Customer ROM Code Release Information AN1754 Data Logging Program for Testing ST7 Applications via ICC 136/139 ST7LITEU05 ST7LITEU09 Description ...

Page 137

... ST7LITEU05 ST7LITEU09 Table 82. ST7 application notes (continued) Identification AN1796 Field Updates for FLASH Based ST7 Applications Using a PC Comm Port AN1900 Hardware Implementation for ST7DALI-EVAL AN1904 ST7MC Three-phase AC Induction Motor Control Software Library AN1905 ST7MC Three-phase BLDC Motor Control Software Library ...

Page 138

... Table 61 on page 106 Table 81 on page 133: added note 4 for ST7MDT10-EMU3, removed Table 60 on page 106 ( Figure 53 Figure 66 on page 117 ST7LITEU05 ST7LITEU09 98, Section 13.8.1 on Section 13.10 on page 118 Table 2 on page 15 Section on page 109 and Figure 54 on page 111 Section 13.4 on page 101 Section 13 ...

Page 139

... ST7LITEU05 ST7LITEU09 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...