ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 36

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

Supply, reset and clock management
7.3.3
7.3.4
Note:
36/139
System integrity (SI) control/status register (SICSR)
Reset Value: 0000 0x00 (0xh)
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits
Bits 4:3 = Reserved, must be kept cleared.
Bits 2:0 = System Integrity bits. Refer to
page
AVD threshold selection register (AVDTHCR)
Reset Value: 0000 0011 (03h)
Bits 7:5 = CK[2:0] internal RC prescaler selection
Table 6.
If the internal RC is used with a supply operating range below 3.3V, a division ratio of at
least 2 must be enabled in the RC prescaler.
Bits 4:2 = Reserved, must be kept cleared.
Bits 1:0 = AVD threshold selection bits. Refer to
(SI) on page
CK2
7
0
7
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately
after reset to adjust the RC oscillator frequency and to obtain the required accuracy.
Refer to
These bits are set by software and cleared by hardware after a reset. These bits select
the prescaler of the internal RC oscillator. See
table and note:
46.
CK2
0
0
0
1
Internal RC prescaler selection bits
46.
CR1
CK1
Section 7.2: Internal RC oscillator adjustment on page
CR0
CK0
others
CK1
0
1
1
0
0
0
Section 8.4: System integrity management (SI) on
Read/write
Read/write
CK0
1
0
1
0
0
0
Section 8.4: System integrity management
Figure 14 on page 34
LVDRF
0
ST7LITEU05 ST7LITEU09
32.
AVDF
AVD1
f
f
f
f
f
RC/16
RC/2
RC/4
RC/8
OSC
f
RC
and the following
AVDIE
AVD0
0
0