ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 117

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

ST7LITEU05 ST7LITEU09
Figure 66. RESET pin protection when LVD is enabled
1. Please refer to
The reset network protects the device against parasitic resets. The output of the external
reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the
RESET pin can go below the V
Otherwise the reset will not be taken into account internally. Because the reset circuit is
designed to allow the internal Reset to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified
for I
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A
10 nF pull-down capacitor is required to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1 M pull-down
resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect
of the power supply (this will add 5µA to the power consumption of the MCU).
Tips when using the LVD
●
●
●
EXTERNAL
conditions
RESET
INJ(RESET)
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100 nF + 1 M pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.”
Required
in
Section 12.2.1: Illegal opcode reset on page 92
0.01 F
Table 46 on page
Table 2 on page 15
1M
Optional
IL
max. level specified in
96.
and notes above).
V
DD
R
ON
Filter
for more details on illegal opcode reset
GENERATOR
Section 13.9.1 on page
PULSE
Electrical characteristics
WATCHDOG
ILLEGAL OPCODE
LVD RESET
INTERNAL
RESET
116.
ST7xxx
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