ST72254G2-Auto STMicroelectronics, ST72254G2-Auto Datasheet
ST72254G2-Auto
Specifications of ST72254G2-Auto
Related parts for ST72254G2-Auto
ST72254G2-Auto Summary of contents
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... Watchdog timer One 16-bit timer - - 3. MHz (with oscillator MHz) -40°C to +85°C / -40°C to +105°C / -40°C to +125C° interfaces SO28 ST72215G2- ST72254G1- ST72254G2- Auto Auto 8 Kbytes 4 Kbytes Two 16-bit timers SPI ADC I2C SO28 Auto 8 Kbytes Rev. 1 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 1 INTRODUCTION The ST72104G-Auto, ST72216G-Auto and ST72254G-Auto devices are members of the ST7 microcontroller family. They can be grouped as follows: – ST72254G-Auto devices are designed for mid- range applications with ADC and I²C interface capabilities. ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 2 PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 RESET 1 28 OSC1 2 27 OSC2 3 26 SS/PB7 MOSI/PB4 22 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to 95. Legend / Abbreviations for Table Type input output supply Input level Dedicated analog input In/Output level: C ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto Pin No. Name 18 PA7 I PA6 /SDAI I PA5 I PA4 /SCLI I PA3 I PA2 I PA1 I PA0 I/O ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 3 REGISTER AND MEMORY MAP As shown in the Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register location, ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto Table 2. Hardware Register Map Register Address Block Label 0000h PCDR 0001h Port C PCDDR 0002h PCOR 0003h 0004h PBDR 0005h Port B PBDDR 0006h PBOR 0007h 0008h PADR 0009h Port A PADDR 000Ah PAOR 000Bh ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto Register Address Block Label 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh TAOC2HR 003Fh TAOC2LR ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 4 FLASH PROGRAM MEMORY 4.1 INTRODUCTION Flash devices have a single voltage non-volatile Flash memory that may be programmed in-situ (or plugged in a programming tool byte-by-byte basis. 4.2 MAIN FEATURES Remote In-Situ Programming ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CPU REGISTERS (cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72104G-Auto, ST72216G-Auto and ST72254G-Auto microcon- trollers include a range of utility features for secur- ing the application in critical situations (for exam- ple, in case of a power brown-out), ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below a V ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto RESET SEQUENCE MANAGER (Cont’d) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an external ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) Read / Write Reset Value: 000x 000x (XXh) 7 LVD Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 6.6 MAIN CLOCK CONTROLLER (MCC) The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be man- aged by the application. All functions ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 7 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto INTERRUPTS (Cont’d) Figure 14. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt Mapping Source No. Block RESET Reset TRAP Software Interrupt 0 ei0 External Interrupt Port A7..0 (C5..0 1 ei1 External Interrupt Port B7..0 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 15). After ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto POWER SAVING MODES (Cont’d) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ST7 HALT instruction (see Figure The MCU can exit HALT mode ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORTS (Cont’d) Figure 20. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORTS (Cont’d) Table 7. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORTS (Cont’d) Caution: The alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts. Analog alternate function When the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORTS (Cont’d) 9.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts HALT cause the device ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values Address (Hex.) Register Label Reset Value of all I/O port registers 0000h PCDR 0001h PCDDR 0002h PCOR 0004h PBDR 0005h PBDDR 0006h PBOR 0008h ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 10 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto MISCELLANEOUS REGISTERS (Cont’d) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS01 IS00 Bit 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h MOD SOD SSM Bit 7:4 = Reserved always read as 0 Bit 3 = MOD SPI ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto WATCHDOG TIMER (Cont’d) Table 11. Watchdog Timing (f CR Register WDG timeout period initial value Max FFh Min C0h Notes: Following a reset, the watchdog is disa- bled. Once activated it cannot be disabled, except by ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto WATCHDOG TIMER (Cont’d) Table 12. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 0024h Reset Value ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 11.2 16-BIT TIMER 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Figure 25. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE OCIE TOIE FOLV2 (See ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +∆t LS Byte ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Figure 26. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 27. Counter Timing Diagram, internal clock divided by 4 CPU ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Figure 29. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 30. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Figure 32. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 33. Output Compare Timing Diagram, ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Figure 34. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 35. Pulse Width Modulation Mode Timing Example COUNTER 34E2 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) 11.2.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag 1. 0: ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 16-BIT TIMER (Cont’d) Table 14. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 11.3 SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 37. Serial Peripheral Interface Block Diagram Read MOSI MISO 8-Bit Shift Register Write SCK SS Internal Bus DR Read Buffer SPIE MASTER CONTROL SERIAL CLOCK GENERATOR MODF SPIF WCOL - - ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4 Functional Description Figure 36 shows the serial peripheral interface (SPI) block diagram. This interface contains three dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 39. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 72/135 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 2 11 BUS INTERFACE (I2C) 11.4.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) 11.4.4 Functional Description Refer to the CR, SR1 and SR2 registers in 11.4.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) Figure 44. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) 11.4.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) 11.4.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK STOP ITE Bit 7:6 = Reserved. ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF ADSL M/SL Bit 7 = EVF Event flag. This bit ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 2 Table 17 Register Map and Reset Values Address Register 7 (Hex.) Label I2CCR 0028h Reset Value 0 I2CSR1 EVF 0029h Reset Value 0 I2CSR2 002Ah Reset Value 0 I2CCCR FM/SM 02Bh Reset Value ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 11.5 8-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is an 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.5.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 18. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 88/135 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto ST7 ADDRESSING MODES (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto ST7 ADDRESSING MODES (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 12.2 INSTRUCTION GROUPS The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- imum values are guaranteed in the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 50. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto OPERATING CONDITIONS (Cont’d) Figure 51. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALITY NOT GUARANTEED 12 IN THIS AREA 2.5 Notes: 1. Guaranteed by construction. A/D operation and ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+ (V rise) DD Reset generation threshold V IT- (V fall) DD ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 55. High LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 Figure 56. Medium LVD Threshold Versus V f [MHz] OSC 16 DEVICE ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.2 WAIT and SLOW WAIT Modes Symbol Parameter Supply current in WAIT mode (see Figure 60) Supply current in SLOW WAIT mode (see Figure 61 Supply current in WAIT mode ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.3 HALT Mode Symbol Parameter I Supply current in HALT mode DD 13.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over tempera- ture range ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3.2 Typical Ceramic Resonators Symbol t Ceramic resonator start-up time SU(osc the typical oscillator start-up time measured between V SU(OSC) struction (with a quick V ramp-up from 0 to ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 64. Typical Application with Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer the typical oscillator ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CLOCK CHARACTERISTICS (Cont’d) 13.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator frequency f OSC External RC oscillator frequency ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CLOCK CHARACTERISTICS (Cont’d) 13.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC f Glitch Filtered Frequency GFOSC Figure 68. Typical Safe Oscillator Frequencies fosc [kHz] -40°C 400 +25°C 350 300 250 200 3.2 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 Flash Program Memory Symbol Parameter T Programming temperature range A(prog) Programming time for ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electromagnetic Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto EMC CHARACTERISTICS (Cont’d) 13.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For ...
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... GENERATOR Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto EMC CHARACTERISTICS (Cont’d) 13.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electrostat- ic Discharge the stress must be controlled to pre- vent degradation or destruction of the circuit ele- ments. The stress generally ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 82. Typical V vs Vol [V] at Iio=2mA 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 Vdd [V] Figure 83. Typical V vs ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Output ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CONTROL PIN CHARACTERISTICS (Cont’d) Figure 86. Typical I vs Ion [µA] Ta=-40°C 200 Ta=25°C 150 100 50 0 3.2 3.5 4 4.5 Vdd [V] Figure 88. Typical V vs Vol ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto CONTROL PIN CHARACTERISTICS (Cont’d) 13.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 89. Two ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 13.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 13.10.2 16-Bit Timer Symbol Parameter t ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.11 COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 91. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter t SCL clock low time ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error T 1) Offset error Gain Error Differential linearity error Integral linearity ...
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... ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 14 PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 96. 28-Pin Plastic Small Outline Package, 300-mil Width ® 14.2 ECOPACK In accordance with the RoHS European directive, all STMicroelectronics packages have been con- verted to lead-free technology, named ECO- ® PACK . ® – ECOPACK ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (Flash) as well as in factory coded versions (ROM). Flash devices are shipped to customers with a default content ...
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... XXX Code name (defined by STMicroelectronics -40 to +85° -40 to +105° -40 to +125° Plastic SOIC ST72104G1, ST72104G2, ST72215G2, ST72216G1, ST72254G1, ST72254G2 A = -40 to +85° -40 to +105° -40 to +125° Plastic SOIC ST72C104G1, ST72C104G2, ST72C215G2, ST72C216G1, ST72C254G1, ST72C254G2 ...
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... HS: High speed resonator ( MHz Network Internal [ ] External [ ] External Clock [ ] Disabled [ ] Enabled [ ] Software Activation [ ] Hardware Activation [ ] Reset [ ] No reset [ ] Disabled [ ] Enabled [ ] Disabled [ ] Enabled ST72254G1 (4KB ST72254G2 (8KB Tube -40°C to +125° Highest threshold [ ] Medium threshold [ ] Lowest threshold 131/135 ...
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... Notes: 1. In-Situ Programming (ISP) interface for Flash devices. 2. Tool equipped with a DIP socket only; an adapter may be required to program devices in SO packages. Table 27. Dedicated STMicroelectronics Development Tools Supported Products ST72254G1, ST72C254G1 ST72254G2, ST72C254G2 ST72215G2, ST72C215G2 ST72216G1, ST72C216G1 ST72104G1, ST72C104G1, ST72104G2, ST72C104G2 132/135 ...
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ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto DEVELOPMENT TOOLS (Cont’d) 15.3.1 Package/Socket Footprint Proposal Table 28. Suggested List of SO28 Socket Types Package / Probe ENPLAS SO28 YAMAICHI EMU PROBE Adapter from SO28 to SDIP32 footprint (delivered with emulator) 15.4 ST7 APPLICATION NOTES ...
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... OPTION LIST” on page vice temperature versions and removed DIP package Section 15.3 "DEVELOPMENT TOOLS" on page the end of the first paragraph Table 26, “STMicroelectronics Tool Features,” on page Section 15.3.1 "Package/Socket Footprint Proposal" on page ed List of SDIP32 Socket Types” Section 15.4 "ST7 APPLICATION NOTES" on page Notes” ...
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... ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...