ST72254G2-Auto STMicroelectronics, ST72254G2-Auto Datasheet - Page 20

• Manufacturer Part Number: ST72254G2-Auto
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72254G2-Auto

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 3 Power Saving Modes: Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx-Auto and ST72216G1- Auto)

ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
Figure 11. RESET Sequences
20/135
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+
IT-
Figure
RUN
V
DD
11).
ON
DELAY
RESET
LVD
weak pull-up resistor.
w(RSTL)out
.
t
t
w(RSTL)out
h(RSTL)in
h(RSTL)in
RUN
DELAY
in
SHORT EXT.
RESET
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
t
h(RSTL)in
Power-On RESET
Voltage Drop RESET
<V
RUN
IT-
(falling edge) as shown in
WATCHDOG UNDERFLOW
DELAY
LONG EXT.
RESET
w(RSTL)out
DD
<V
RUN
DD
IT+
INTERNAL RESET (4096 T
FETCH VECTOR
.
larger than t
DELAY
(rising edge) or
WATCHDOG
RESET
t
w(RSTL)out
Figure
Figure
g(VDD)
11.
RUN
CPU
11.
)
to