ST72254G2-Auto STMicroelectronics, ST72254G2-Auto Datasheet - Page 19
ST72254G2-Auto
Manufacturer Part Number
ST72254G2-Auto
Description
8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, I2C interfaces
Manufacturer
STMicroelectronics
Datasheet
1.ST72254G2-AUTO.pdf
(135 pages)
Specifications of ST72254G2-Auto
Clock Sources
crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
3 Power Saving Modes
Halt, Wait and Slow
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx-Auto and ST72216G1- Auto)
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6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of three
phases as shown in
■
■
■
Figure 10. Reset Block Diagram
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Delay depending on the RESET source
4096 CPU clock cycle delay
RESET vector fetch
RESET
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
Figure
Figure
V
9:
DD
R
ON
10:
f
CPU
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 9. RESET Sequence Phases
DELAY
4096 CLOCK CYCLES
INTERNAL RESET
RESET
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
VECTOR
FETCH
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