ST72254G2-Auto STMicroelectronics, ST72254G2-Auto Datasheet - Page 39

• Manufacturer Part Number: ST72254G2-Auto
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72254G2-Auto

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 3 Power Saving Modes: Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx-Auto and ST72216G1- Auto)

11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■
■
■
■
■
Figure 24. Watchdog Block Diagram
Programmable timer (64 increments of 12288
CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
Optional
(configurable by option byte)
Hardware Watchdog selectable by option byte
reset
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
f
CPU
on
HALT
WDGA
RESET
T6
instruction
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
CLOCK DIVIDER
T4
11.1.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the RESET pin for typical-
ly 30µs.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T5:T0 bits contain the number of increments
diate reset
which represents the time delay before the
watchdog produces a reset.
÷12288
T3
Table 11 Watchdog Timing (fCPU = 8
T2
T1
T0
MHz)):
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