ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 140

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ST92150JDV1QAuto

Manufacturer Part Number
ST92150JDV1QAuto
Description
8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92150JDV1QAuto

Internal Memory
Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
Minimum Instruction Time
83 ns (24 MHz int. clock)
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
7.6 RESET/STOP MANAGER
The Reset/Stop Manager resets the MCU when
one of the three following events occurs:
– A Hardware reset, initiated by a low level on the
– A Software reset, initiated by a HALT instruction
– A Watchdog end of count condition.
The event which caused the last Reset is flagged
in the CLK_FLAG register, by setting either the
Figure 70. Oscillator Start-up Sequence and Reset Timing
140/430
9
Reset pin.
(when enabled with the SRESEN bit of the
CLKCTL register).
V
OSCIN
OSCOUT
INTCLK
RESET
PIN
V
DD
DD
MAX
MIN
T
STUP
SOFTRES or the WDGRES bit or both; a hard-
ware initiated reset will leave both these bits reset.
The hardware reset overrides all other conditions
and forces the ST9 to the reset state. During Re-
set, the internal registers are set to their reset val-
ues (when these reset values are defined, other-
wise the register content will remain unchanged),
and the I/O pins are set to Bidirectional Weak-Pull-
Up or High impedance input. See
Reset is asynchronous: as soon as the reset pin is
driven low, a Reset cycle is initiated.
Section
VR02085A
7.3.

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