ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 179

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

EXTENDED FUNCTION TIMER (Cont’d)
10.3.4 Interrupt Management
The interrupts of the Extended Function Timer are
mapped on one of the eight External Interrupt
Channels of the microcontroller (refer to the “Inter-
rupts” chapter).
The three interrupt sources are mapped on the
same interrupt channel. To use them, the EFTIS
bit must be set)
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
– A pending bit in the EIPR register (R243 - Page
– A mask bit in the EIMR register (R244 - Page 0).
Program the interrupt priority level using the EI-
PLR register (R245 - Page 0). For a description of
these registers refer to the “Interrupts” and “DMA”
chapters.
Using the external interrupt channel for all EFT
interrupts
To use the interrupt features, perform the following
sequence:
– Set the priority level of the interrupt channel used
– Select the interrupt trigger edge as rising edge
– Set the EFTIS bit of the CR3 register to select
Page 0),
0),
(EIPLR register)
(set the corresponding bit in the EITR register)
the peripheral interrupt sources
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
– Set the OCIE (or OC1IE/OC2IE bits) and/or ICIE
– In the EIPR register, reset the pending bit of the
– Set the mask bits of the interrupt channels used
– Clear all EFT interrupt flags by reading the Sta-
Caution:
1. It is mandatory to clear all EFT interrupt flags
2. Since a loop statement is needed inside the IT
(or IC1IE/IC2IE bits and/or TOIE bit(s) in the CR1
register to enable interrupts
interrupt channel used by the peripheral inter-
rupts to avoid any spurious interrupt requests be-
ing performed when the mask bit is set
to enable the MCU to acknowledge the interrupt
requests of the peripheral.
tus, Input Capture Low, Output Compare Low
and Counter Low Registers.
simultaneously at least once before exiting an
EFT timer interrupt routine (the SR register
must = 00h at some point during the interrupt
routine), otherwise no interrupts can be issued
on that channel anymore.
Refer to the following assembly code for an
interrupt sequence example.
routine, the user must avoid situations where
an interrupt event period is narrower than the
duration of the interrupt treatment. Otherwise
nested interrupt mode must be used to serve
higher priority requests.
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