ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 56

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
3.3 REGISTER DESCRIPTION
3.3.1 Control Registers
FLASH CONTROL REGISTER (FCR)
Address: 224000h / 221000h- Read/Write
Reset value: 0000 0000 (00h)
The Flash Control Register is used to enable all
the operations for the Flash and the TestFlash
memories.
Bit 7 = FWMS: Flash Write Mode Start (Read/
Write).
This bit must be set to start each write/erase oper-
ation in Flash memory. At the end of the write/
erase operation or during a Sector Erase Suspend
this bit is automatically reset. To resume a sus-
pended Sector Erase operation, this bit must be
set again. Resetting this bit by software does not
stop the current write operation.
0: No effect
1: Start Flash write
Bit 6 = FPAGE: Flash Page program (Read/Write).
This bit must be set to select the Page Program
operation in Flash memory. This bit is automatical-
ly reset at the end of the Page Program operation.
The Page Program operation allows to program
“0”s in place of “1”s. From 1 to 16 bytes can be en-
tered (in any order, no need for an ordered ad-
dress sequence) before starting the execution by
setting the FWMS bit. All the addresses must be-
long to the same page (only the 4 LSBs of address
can change). Data to be programmed and ad-
dresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged.
0: Deselect page program
1: Select page program
Bit 5 = FCHIP: Flash CHIP erase (Read/Write).
This bit must be set to select the Chip Erase oper-
ation in Flash memory. This bit is automatically re-
set at the end of the Chip Erase operation.
The Chip Erase operation erases all the Flash lo-
cations to FFh. The operation is limited to Flash
56/430
FWMS FPAGE FCHIP FBYTE FSECT FSUSP PROT FBUSY
9
7
6
5
4
3
2
1
0
code: sectors F0-F3 (or F0-F5 for the ST92250-
Auto), TestFlash and
tion starts by setting the FWMS bit. It is not neces-
sary to pre-program the sectors to 00h, because
this is done automatically.
0: Deselect chip erase
1: Select chip erase
Bit 4 = FBYTE: Flash byte program (Read/Write).
This bit must be set to select the Byte Program op-
eration in Flash memory. This bit is automatically
reset at the end of the Byte Program operation.
The Byte Program operation allows “0”s to be pro-
grammed in place of “1”s. Data to be programmed
and an address in which to program must be pro-
vided (through an LD instruction, for example) be-
fore starting execution by setting bit FWMS.
0: Deselect byte program
1: Select byte program
Bit 3 = FSECT: Flash sector erase (Read/Write).
This bit must be set to select the Sector Erase op-
eration in Flash memory. This bit is automatically
reset at the end of the Sector Erase operation.
The Sector Erase operation erases all the Flash
locations to FFh. From 1 to 6 sectors (F0-F5) can
be simultaneously erased. These sectors can be
entered before starting the execution by setting
the FWMS bit. An address located in the sector to
erase must be provided (through an LD instruc-
tion, for example), while the data to be provided is
don’t care. It is not necessary to pre-program the
sectors to 00h, because this is done automatically.
0: Deselect sector erase
1: Select sector erase
Bit 2 = FSUSP: Flash sector erase suspend
(Read/Write).
This bit must be set to suspend the current Sector
Erase operation in Flash memory in order to read
data to or from program data to a sector not being
erased. The FSUSP bit must be reset (and FWMS
must be set again) to resume a suspended Sector
Erase operation.
The Erase Suspend operation resets the Flash
memory to normal read mode (automatically reset-
ting bit FBUSY) in a maximum time of 15µs.
E
3 TM
excluded. The execu-