ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 177

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
Procedure
To use pulse width modulation mode select the fol-
lowing in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
And select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated
– Set the PWM bit.
– Select the timer clock CC[1:0] bits (see
Load the OC2R register with the value corre-
sponding to the period of the signal.
Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
The OC
ing application can be calculated using the follow-
ing formula:
Where:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See
plied to the OCMP1 pin after a successful com-
parison with OC1R register.
plied to the OCMP1 pin after a successful com-
parison with OC2R register.
to the output compare 1 function.
36).
– t = Desired output compare period (seconds)
–
– CC1-CC0 = Timer clock prescaler
INTCLK
i
R register value required for a specific tim-
OCiR Value =
= Internal clock frequency
CC[1:0]
t
* INTCLK
Figure
- 5
100).
Table
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Notes:
– After a write instruction to the OCiHR register,
– The OCF1 bit cannot be set by hardware in PWM
– The Input Capture function is available in PWM
– When Counter = OC2R, then the OCF2 bit will be
– When the Pulse Width Modulation (PWM) and
– The value loaded in register OC2R must always
– When OC1R >OC2R, no waveform will be gen-
– When OC2R = OC1R, a square waveform will
– When OC2R is loaded with FFFC (the counter
– When OC1R is loaded with FFFC (the counter
– When FOLV1 bit is set and PWM bit is set, then
the output compare function is inhibited until the
OCiLR register is also written.
mode, but the OCF2 bit is set every time the
counter matches the OC2R register.
mode.
set. This can generate an interrupt if OCIE is set
or OCIE is reset and OC2IE is set. This interrupt
is useful in applications where the pulse-width or
period needs to be changed interactively.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active mode.
be greater than the value in register OC1R in or-
der to produce meaningful waveforms. Note that
0000h is considerred to be greater than FFFCh
or FFFDh or FFFEh or FFFFh.
erated.
be generated as in
reset value) then no waveform will be generated
& the counter will remain stuck at FFFC.
reset value) then the waveform will be generated
as in
PWM mode is the active one. But if FOLV2 bit is
set then the OLVL2 bit will appear on OCMP2
(when OC2E bit = 1).
Figure 100
Counter
= OC1R
Counter
= OC2R
When
When
Pulse Width Modulation cycle
Figure 100
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
to FFFCh
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