ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet
ST7232AK2-Auto
Specifications of ST7232AK2-Auto
Related parts for ST7232AK2-Auto
ST7232AK2-Auto Summary of contents
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... ST7232AK2-Auto ROM 8K ST7232AJ1-Auto ROM 4K ST7232AJ2-Auto ROM 8K January 2008 ST7232AK1-Auto ST7232AK2-Auto ST7232AJ1-Auto ST7232AJ2-Auto 10-bit ADC, 4 timers, SPI, SCI – Main clock controller with: real time base, beep and clock-out capabilities – Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 output compares, PWM and pulse generator modes ■ ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7232Axx-Auto 6.5 Reset sequence manager (RSM 6.5.1 6.5.2 ...
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Contents 9.2.1 9.2.2 9.2.3 9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7232Axx-Auto 10.4 Serial peripheral interface (SPI 103 10.4.1 10.4.2 ...
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Contents 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ...
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ST7232Axx-Auto 12.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175 12.11.1 SPI (serial peripheral interface ...
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Contents 15.2 ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7232Axx-Auto List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 103. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 104. FASTROM factory coded device types 189 Table 105. ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 106. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 107. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 108. Port A and F configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 109 ...
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List of figures List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7232Axx-Auto Figure 49. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Introduction 1.1 Description The ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto devices are members of the ST7 microcontroller family designed for the 5V operating range. The 32 and 44-pin devices are designed for mid-range applications All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. ...
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... Principal differences ● Minor content differences ● Editing and formatting differences 1.2.1 Principal differences 1. Changed root part number from ST7232A to ST7232AK1-Auto, ST7232AK2-Auto, ST7232AJ1-Auto, and ST7232AJ2-Auto throughout document 2. Changed document title 3. Removed 1 and 5 suffix version temperatures ranges throughout the document 4. Features on page and changed the condition ...
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Introduction 18. Table 85: ESD absolute maximum ratings on page – Added test standards to conditions column Changed max value of CDM from 250 V to: > 500 V to ≤ 750 V with corner pins > – 750 V ...
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... Table 105: ROM factory coded device types on page 190 18. Updated Figure 90: ROM commercial product code structure on page 190 19. Updated ST72P32A/ST7232A (3.8 to 5.5V) microcontroller option list on page 191 20. Updated Table 106: STMicroelectronics development tools on page 193 21. Section 14.4: Development tools on page – Updated – Deleted – ...
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Introduction 1.2.3 Editing and formatting differences 1. Reformatted document 2. Converted register and bit decriptions to table format 3. Edited English throughout document 4. Correctly aligned footnotes of tables throughout document 18/201 ST7232Axx-Auto ...
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ST7232Axx-Auto 2 Pin description Figure 2. 32-pin LQFP 7x7 package pinout 1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector AREF ei3 ei2 V 2 ...
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Pin description Figure 3. 44-pin LQFP package pinout 1. Legend: (HS) = 20mA high sink capability; eix = associated external interrupt vector For external pin connection guidelines, refer to page 153. In Table 2: Device pin description details on the ...
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ST7232Axx-Auto Table 2. Device pin description Pin no. Pin name 6 30 PB4 (HS) I PD0/AIN0 I PD1/AIN1 I PD2/AIN2 I PD3/AIN3 I/O C (4) 11 ...
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Pin description Table 2. Device pin description Pin no. Pin name 30 15 PC7/SS/AIN15 I PA3 (HS) I DD_1 ( SS_1 34 17 PA4 (HS) I/O C ...
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ST7232Axx-Auto 3. ‘T’ defines a true open drain I/O (P-buffer and protection diode to V page 62 and Section 12.8: I/O port pin characteristics 4. Each I/O port has 8 pads. Pads that are not bonded to external pins are ...
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Register and memory map 3 Register and memory map As shown in <Blue HT>Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up ...
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ST7232Axx-Auto Table 3. Hardware register map Address Block Register label 0000h PADR (3) 0001h Port A PADDR 0002h PAOR 0003h PBDR (3) 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDADR (3) 000Ah ...
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Register and memory map Table 3. Hardware register map (continued) Address Block Register label 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h Timer A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR ...
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ST7232Axx-Auto 4 Flash program memory 4.1 Introduction The ST7 dual voltage high density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using ...
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Flash program memory 4.3.1 Read-out protection Read-out protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very ...
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... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see to the device pinout description ...
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Flash program memory 4.6 In-application programming (IAP) This mode uses a Bootloader program previously stored in sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user ...
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ST7232Axx-Auto 5 Central processing unit 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 Main features ● Enable executing 63 basic instructions ● Fast 8-bit by 8-bit multiply ● ...
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Central processing unit Accumulator (A) The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index registers (X and Y) These 8-bit registers are used ...
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ST7232Axx-Auto Table 6. CC register description Bit Bit name 5,3 I1 Interrupt management bits - interrupt The combination of the I1 and I0 bits gives the current interrupt software priority: 10: Interrupt software priority = ...
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Central processing unit Stack pointer register (SP The stack pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after data has been pushed ...
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ST7232Axx-Auto Figure 8. Stack manipulation example Call subroutine @ 0100h SP PCH PCL @ 01FFh 1. Legend: stack higher addres = 01FFh; stack lower address = 0100h PUSH Y Interrupt event ...
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Supply, reset and clock management 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number ...
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ST7232Axx-Auto Figure 10. Clock, reset and supply block diagram OSC2 Multi-oscillator (MO) OSC1 Reset sequence manager RESET (RSM 6.4 Multi-oscillator (MO) The main clock of the ST7 can be generated by two different source types coming ...
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Supply, reset and clock management Table 7. ST7 clock source 6.5 Reset sequence manager (RSM) 6.5.1 Introduction The reset sequence manager includes two reset sources as shown in ● External RESET source pulse ● Internal watchdog reset These sources act ...
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ST7232Axx-Auto Figure 11. Reset sequence phases 6.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. ...
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Supply, reset and clock management 6.5.4 Internal watchdog reset The reset sequence generated by a internal watchdog counter overflow is shown in Figure 13. Starting from the watchdog counter underflow, the device RESET pin acts as an output that is ...
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ST7232Axx-Auto 6.6 System integrity management System integrity control/status register (SICSR) SICSR 7 6 Table 8. SICSR register description Bit Bit name 7:1 0 WDGRF 5 4 Reserved - Reserved, must be kept cleared - Watchdog reset flag This bit indicates ...
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Interrupts 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...
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ST7232Axx-Auto Table 9. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 14. Interrupt processing flowchart Reset Restore PC from stack Level Low High Pending Y ...
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Interrupts 7.2.1 Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: ● the highest software priority interrupt is serviced ● if several ...
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ST7232Axx-Auto 7.2.3 Non-maskable sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 14). After stacking the PC and CC registers (except for reset), the corresponding vector ...
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Interrupts 7.3 Interrupts and low power modes All interrupts allow the processor to exit the wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ‘exit ...
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ST7232Axx-Auto Figure 17. Nested interrupt management RIM MAIN 11/10 7.5 Interrupt registers CPU CC register interrupt bits CPU R/W Table 10. CPU CC register description Bit Bit name TRAP and reset ...
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Interrupts Interrupt software priority registers (ISPRX) ISPR0 7 6 I1_3 I0_3 R/W R/W ISPR1 7 6 I1_7 I0_7 R/W R/W ISPR2 7 6 I1_11 I0_11 R/W R/W ISPR3 These four registers contain the interrupt ...
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ST7232Axx-Auto 7.6 Interrupt related instructions Table 12. Dedicated interrupt instruction set Instruction HALT Entering halt mode IRET Interrupt routine return JRM Jump if I1 (level 3) JRNM Jump if I1:0 <> 11 POP CC Pop CC from the ...
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Interrupts Figure 18. External interrupt control bits Port A3 interrupt PAOR.3 PADDR.3 PA3 IPA bit Port F [2:0] interrupts PFOR.2 PFDDR.2 PF2 Port B [3:0] interrupts PBOR.3 PBDDR.3 PB3 IPB bit Port B [7:4] interrupts PBOR.7 PBDDR.7 PB7 50/201 EICR ...
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ST7232Axx-Auto 7.8 External interrupt control register (EICR) EICR 7 6 IS1[1:0] R/W Table 13. EICR register description Bit Bit name 7:6 IS1[1: IPB IS2[1:0] R/W R/W Interrupt sensitivity (ei2 and ei3) The interrupt sensitivity, defined using the ...
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Interrupts Table 13. EICR register description (continued) Bit Bit name 4:3 IS2[1:0] 2 1:0 52/201 Interrupt sensitivity (ei0 and ei1) The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: External interrupt ei0 (port A[3:0]): ...
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ST7232Axx-Auto 7.9 Nested interrupts register map and reset value Table 14. Nested interrupts register map and reset values Address (Hex.) Register label ISPR0 0024h Reset value ISPR1 0025h Reset value ISPR2 0026h Reset value ISPR3 0027h Reset value EICR 0028h ...
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Power saving modes 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see wait), active halt and halt. ...
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ST7232Axx-Auto Figure 20. Slow mode clock transitions 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. ...
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Power saving modes Figure 21. Wait mode flow-chart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine ...
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ST7232Axx-Auto 8.4.1 Active halt mode Active halt mode is the lowest power consumption mode of the MCU with a real-time clock available entered by executing the ‘HALT’ instruction when the OIE bit of the main clock controller status ...
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Power saving modes Figure 23. Active halt mode flow-chart 1. Peripheral clocked with an external clock source can still be active 2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from active halt mode (such as ...
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ST7232Axx-Auto The compatibility of watchdog operation with halt mode is configured by the ‘WDGHALT’ option bit of the option byte. The HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see details. Figure 24. ...
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Power saving modes Figure 25. Halt mode flow-chart 1. WDGHALT is an option bit. See 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from halt mode (such ...
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ST7232Axx-Auto Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from halt mode ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as ‘input pull-up with ...
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I/O ports 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● Transfer of data through digital inputs and outputs For specific pins they offer different functional modes: ● External interrupt generation ● Alternate signal input/output for ...
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ST7232Axx-Auto External interrupt function When an I/O is configured as input with interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently ...
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I/O ports Figure 26. I/O port general block diagram Register Alternate access output Alternate enable DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 External interrupt source ( Table 18. I/O port mode options ...
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ST7232Axx-Auto Table 19. I/O port configurations Not implemented in true open drain I/O ports Pad Not implemented in true open drain I/O ports Pad Not implemented in true open drain I/O ports Pad 1. When the I/O port is in ...
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I/O ports Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to ...
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ST7232Axx-Auto Table 20. Port register configurations Port Pin name PA[7:6] Port A PA[5:4] PA[3] PB[3] Port B PB[4] PB[2:0] Port C PC[7:0] Port D PD[5:0] Port E PE[1:0] PF[7:6] PF[4] Port F PF[2] PF[1:0] 9.4 Low power modes Table 21. ...
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I/O ports Table 23. I/O port register map and reset values Address (Hex.) Reset value of all I/O port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR ...
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ST7232Axx-Auto 10 On-chip peripherals 10.1 Watchdog timer (WDG) 10.1.1 Introduction The watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon ...
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On-chip peripherals Figure 28. Watchdog block diagram f OSC2 MCC/RTC DIV 64 12-bit MCC RTC counter MSB 11 6 10.1.4 How to program the watchdog timeout Figure 29 shows the linear relationship between the 6-bit value to be loaded in ...
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ST7232Axx-Auto Figure 30. Exact timeout duration (t : Where t = (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT = value ...
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On-chip peripherals 10.1.5 Low power modes Table 24. Effect of low power modes on watchdog timer Mode Slow No effect on watchdog. Wait No effect on watchdog. OIE bit in MCCSR register 0 Halt 0 1 10.1.6 Hardware watchdog option ...
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ST7232Axx-Auto 10.1.9 Control register (WDGCR) WDGCR 7 6 WDGA R/W Table 25. WDGCR register description Bit Bit name 7 WDGA 6:0 T[6:0] 1. The WDGA bit is not used if the hardware watchdog option is enabled by option byte. 10.1.10 ...
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On-chip peripherals 10.2.2 Clock-out capability The clock-out capability is an alternate function of an I/O port pin that outputs drive external devices controlled by the MCO bit in the MCCSR register. Caution: When selected, the ...
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ST7232Axx-Auto 10.2.5 Low power modes Table 27. Effect of low power modes on MCC/RTC Mode Wait Active halt Halt 10.2.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the ...
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On-chip peripherals 10.2.7 MCC/RTC registers MCC control/status register (MCCSR) MCCSR 7 6 MCO R/W Table 29. MCCSR register description Bit Bit name 7 MCO 6:5 CP[1:0] 4 SMS 3:2 TB[1:0] 76/201 5 4 CP[1:0] SMS R/W R/W Main clock out ...
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ST7232Axx-Auto Table 29. MCCSR register description (continued) Bit Bit name 1 0 MCC beep control register (MCCBCR) MCCBCR 7 6 Table 30. MCCBCR register description Bit Bit name 7:2 1:0 BC[1:0] Oscillator interrupt enable This bit set and cleared by ...
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On-chip peripherals 10.2.8 MCC register map and reset values Table 31. Main clock controller register map and reset values Address(Hex.) MCCSR 002Ch Reset value MCCBCR 002Dh Reset value 10.3 16-bit timer 10.3.1 Introduction The timer consists of a 16-bit free-running ...
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ST7232Axx-Auto ● Reduced power mode ● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK) The block diagram is shown in 10.3.3 Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter ...
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On-chip peripherals Figure 32. Timer block diagram f CPU 8 high EXEDG 1/2 Counter register 1/4 1/8 EXTCLK pin Alternate counter CC[1:0] Overflow detect circuit ICF1 OCF1 TOF ICF2 CSR (control/status register) ICIE OCIE TOIE FOLV2 (1) Timer interrupt 1. ...
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ST7232Axx-Auto 16-bit read sequence (from either the counter register or alternate counter register) Figure 33. 16-bit read sequence The user must read the MS byte first, then the LS byte value is buffered automatically. This buffered value remains unchanged until ...
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On-chip peripherals External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on ...
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ST7232Axx-Auto Input capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value ...
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On-chip peripherals Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi is never set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds ...
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ST7232Axx-Auto Figure 38. Input capture timing diagram Timer clock Counter register ICAPi pin ICAPi flag ICAPi register 1. The rising edge is the active edge. Output compare In this section, the index, i, may because there ...
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On-chip peripherals When a match is found between OCRi register and CR register: ● OCFi bit is set ● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset) ● A timer interrupt is generated ...
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ST7232Axx-Auto Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is a general I/O ...
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On-chip peripherals Figure 40. Output compare timing diagram, f Output compare register i (OCRi) Output compare flag i (OCFi) Figure 41. Output compare timing diagram, f Output compare register i (OCRi) 88/201 Internal CPU clock Timer clock Counter register 2ECF ...
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ST7232Axx-Auto One pulse mode One pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the input capture1 function and ...
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On-chip peripherals The OC1R register value required for a specific timing application can be calculated using the following formula: Where Pulse period (in seconds CPU clock frequency (in hertz) CPU = Timer prescaler factor (2, 4 ...
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ST7232Axx-Auto Figure 43. One pulse mode timing example IC1R Counter ICAP1 OCMP1 1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 44. Pulse width modulation mode timing example with 2 output compare functions Counter 34E2 ...
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On-chip peripherals Pulse width modulation mode Pulse width modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse width modulation mode uses the complete ...
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ST7232Axx-Auto The OC R register value required for a specific timing application can be calculated using i the following formula:: Where Signal or pulse period (in seconds CPU clock frequency (in hertz) CPU = Timer prescaler ...
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On-chip peripherals 10.3.4 Low power modes Table 32. Effect of low power modes on 16-bit timer Mode No effect on 16-bit timer. Wait Timer interrupts cause the device to exit from wait mode. 16-bit timer registers are frozen. In halt ...
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ST7232Axx-Auto 10.3.6 Summary of timer modes Table 34. Summary of timer modes Modes (1) Input capture and/or (1) Output compare and/or One pulse mode PWM mode 1. See note 4 in One pulse mode on page 89 2. See note ...
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On-chip peripherals Table 35. CR1 register description (continued) Bit Bit name 4 FOLV2 3 FOLV1 2 OLVL2 1 IEDG1 0 OLVL1 96/201 Function Forced output compare 2 This bit is set and cleared by software effect on the ...
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ST7232Axx-Auto Control register 2 (CR2) CR2 7 6 OC1E OC2E R/W R/W Table 36. CR2 register description Bit Bit name 7 OCIE 6 OC2E 5 OPM 4 PWM 3:2 CC[1: OPM PWM CC[1:0] R/W R/W R/W Function ...
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On-chip peripherals Table 36. CR2 register description (continued) Bit Bit name 1 IEDG2 0 EXEDG Control/status register (CSR) CSR 7 6 ICF1 OCF1 R R Table 37. CSR register description Bit Bit name 7 ICF1 6 OCF1 5 TOF 4 ...
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ST7232Axx-Auto Table 37. CSR register description (continued) Bit Bit name 3 OCF2 2 TIMD 1:0 Input capture 1 high register (IC1HR) This is an 8-bit read only register that contains the high part of the counter value (transferred by the ...
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On-chip peripherals Output compare 1 low register (OC1LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC1LR 7 6 MSB R/W R/W Output compare 2 high register (OC2HR) ...
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ST7232Axx-Auto Counter low register (CLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF ...
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On-chip peripherals Input capture 2 low register (IC2LR) This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). IC2LR 7 6 MSB R R 16-bit timer register ...
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ST7232Axx-Auto 10.4 Serial peripheral interface (SPI) 10.4.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not ...
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On-chip peripherals Figure 46. Serial peripheral interface block diagram SPIDR Read buffer MOSI MISO 8-bit shift register SOD bit SCK SS Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure ...
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ST7232Axx-Auto Figure 47. Single master/single slave application Master MSbit 8-bit shift register SPI clock generator Slave select management As an alternative to using the SS pin to control the slave select signal, the application can choose to manage the slave ...
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On-chip peripherals Figure 48. Generic SS timing diagram MOSI/MISO Master SS Slave SS if CPHA = 0 Slave SS if CPHA = 1 Figure 49. Hardware/software slave select management Master mode operation In master mode, the serial clock is output ...
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ST7232Axx-Auto Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the most significant bit of the MOSI pin first. When data transfer ...
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On-chip peripherals The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see (OVR) on page 110). 10.4.4 Clock phase and clock polarity ...
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ST7232Axx-Auto Figure 50. Data clock timing diagram SCK (CPOL = 1) SCK (CPOL = 0) MISO MSbit (from master) MOS1 MSbit (from slave) SS (to slave) Capture strobe SCK (CPOL = 1) SCK (CPOL = 0) MISO MSbit (from master) ...
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On-chip peripherals 10.4.5 Error flags Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a master mode fault occurs: ● The MODF bit is set and an SPI interrupt request ...
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ST7232Axx-Auto Figure 51. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st step 2nd step 1. Writing to the SPIDR register instead of reading it does not ...
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On-chip peripherals Figure 52. Single master/multiple slave configuration SCK Slave MCU MOSI MOSI SCK Master MCU 5V SS 10.4.6 Low power modes Table 39. Effect of low power modes on SPI Mode Wait Halt Using the SPI to wakeup the ...
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ST7232Axx-Auto 10.4.7 Interrupts Table 40. SPI interrupt control/wake-up capability Interrupt event SPI end of transfer event Master mode fault event Overrun error 1. The SPI interrupt events are connected to the same interrupt vector (see generate an interrupt if the ...
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On-chip peripherals Table 41. SPICR register description (continued) Bit Bit name 4 MSTR 3 CPOL 2 CPHA 1:0 SPR[1:0] 114/201 Function Master mode This bit is set and cleared by software also cleared by hardware when, in master ...
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ST7232Axx-Auto Control/status register (SPICSR) SPICSR 7 6 SPIF WCOL R R Table 42. SPICSR register description Bit Bit name 7 SPIF 6 WCOL 5 OVR 4 MODF 3 2 SOD 5 4 OVR MODF R R R/W Serial peripheral data ...
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On-chip peripherals Table 42. SPICSR register description (continued) Bit Bit name 1 SSM 0 Data I/O register (SPIDR) SPIDR 7 6 The SPIDR register is used to transmit and receive data on the serial bus master device, a ...
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ST7232Axx-Auto SPI register map and reset values Table 43. SPI register map and reset values Addres (Hex.) Register label SPIDR 0021h Reset value SPICR 0022h Reset value SPICSR 0023h Reset value 10.5 Serial communications interface (SCI) 10.5.1 Introduction The serial ...
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On-chip peripherals ● Parity control: – Transmits parity bit – Checks parity of received data byte ● Reduced power consumption mode 10.5.3 General description The interface is externally connected to another device by two pins (see ● TDO: Transmit data ...
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ST7232Axx-Auto Figure 53. SCI block diagram Write Transmit data register (TDR) TDO Transmit shift register RDI Transmit control CR2 TIE TCIE RIE SCI interrupt control Transmitter clock f CPU Read Received data register (RDR SCID Wake up unit ...
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On-chip peripherals 10.5.4 Functional description The block diagram of the serial control interface, is shown in dedicated registers: ● Two control registers (SCICR1 and SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) ● An extended prescaler ...
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ST7232Axx-Auto Figure 54. Word length programming 9-bit word length (M bit is set) Start Bit0 bit 8-bit word length (M bit is reset) Start bit Transmitter The transmitter can send data words of either bits depending on ...
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On-chip peripherals The TDRE bit is set by hardware and it indicates: ● The TDR register is empty ● The data transfer is beginning ● The next data can be written in the SCIDR register without overwriting the previous data ...
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ST7232Axx-Auto Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception ...
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On-chip peripherals Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF ...
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ST7232Axx-Auto Figure 55. SCI baud rate and extended prescaler block diagram f CPU /16 /PR SCP1 Extended prescaler transmitter rate control SCIETPR Extended transmitter prescaler register SCIERPR Extended receiver prescaler register Extended prescaler receiver rate control Extended prescaler Transmitter rate ...
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On-chip peripherals Framing error A framing error is detected when: ● The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. ● A break is received When the framing error ...
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ST7232Axx-Auto The baud rates are calculated as follows: where: ETPR = 1,..,255 (see page 137) ERPR = 1,.. 255 (see Receiver muting and wake up feature In multiprocessor configurations it is often desirable that only the intended message recipient should ...
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On-chip peripherals Table 44. Frame formats M bit Legend start bit, STB = stop bit parity bit. Note: In case of wake address mark, the MSB bit of ...
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ST7232Axx-Auto Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: ...
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On-chip peripherals Figure 56. Bit sampling in reception mode RDI line Sample clock 1 10.5.5 Low power modes Table 45. Effect of low power modes on SCI Mode Wait Halt 10.5.6 Interrupts Table 46. SCI interrupt control/wake-up capability Interrupt event ...
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ST7232Axx-Auto 10.5.7 SCI registers Status register (SCISR) SCISR 7 6 TDRE Table 47. SCISR register description Bit Bit name 7 TDRE 6 5 RDRF 4 IDLE 5 4 RDRF IDLE R R Transmit data register empty This ...
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On-chip peripherals Table 47. SCISR register description (continued) Bit Bit name 132/201 Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into ...
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ST7232Axx-Auto Control register 1 (SCICR1) SCICR1 R/W R/W Table 48. SCICR1 register description Bit Bit name SCID 4 3 WAKE 2 PCE 5 4 SCID M WAKE R/W R/W Receive data bit 8 ...
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On-chip peripherals Table 48. SCICR1 register description (continued) Bit Bit name 1 0 Control register 2 (SCICR2) SCICR2 7 6 TIE TCIE R/W R/W Table 49. SCICR2 register description Bit Bit name 7 6 TCIE 5 4 134/201 Parity selection ...
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ST7232Axx-Auto Table 49. SCICR2 register description (continued) Bit Bit name RWU 0 SBK Data register (SCIDR) Contains the received or transmitted data character, depending on whether it is read from or written to. SCIDR 7 6 The ...
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On-chip peripherals Baud rate register (SCIBRR) SCIBRR 7 6 SCP[1:0] R/W Table 50. SCIBRR register description Bit Bit name 7:6 SCP[1:0] 5:3 SCT[2:0] 2:0 SCR[2:0] 136/201 SCT[2:0] R/W Function First SCI prescaler These 2 prescaling bits allow ...
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ST7232Axx-Auto Extended receive prescaler division register (SCIERPR) Allows setting of the extended prescaler rate division factor for the receive circuit. SCIERPR 7 6 Table 51. SCIERPR register description Bit Bit name 7:0 ERPR[7:0] Extended transmit prescaler division register (SCIETPR) Allows ...
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On-chip peripherals Baud rate selection Table 53. Baud rate selection Symbol Parameter f Communication Tx f frequency Rx SCI register map and reset values Table 54. SCI register map and reset values Address (Hex.) Register label SCISR 0050h Reset value ...
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ST7232Axx-Auto 10.6 10-bit A/D converter (ADC) 10.6.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...
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On-chip peripherals 10.6.3 Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not decrease and never increases if the analog input does not increase. If the input voltage (V conversion result is ...
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ST7232Axx-Auto Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly ...
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On-chip peripherals Table 56. ADCCSR register description (continued) Bit Bit name 4 3:0 CH[3:0] Data register (ADCDRH) ADCDRH 7 6 Table 57. ADCDRH register description Bit Bit name 7:0 D[9:2] Data register (ADCDRL) ADCDRL 7 6 142/201 0 Reserved, must ...
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ST7232Axx-Auto Table 58. ADCDRL register description Bit Bit name 7:2 1:0 D[1:0] ADC register map and reset value Table 59. ADC register map and reset values Address (Hex.) ADCCSR 0070h Reset value ADCDRH 0071h Reset value ADCDRL 0072h Reset value ...
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Instruction set 11 Instruction set 11.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups (see Table 60). Table 60. CPU addressing mode groups Addressing mode Inherent Immediate Direct Indexed Indirect ...
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ST7232Axx-Auto Table 61. CPU addressing mode overview Mode Inherent Immediate Short Direct Long Direct No offset Direct Short Direct Long Direct Short Indirect Long Indirect Short Indirect Indexed ld A,([$10],X) Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit ...
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Instruction set 11.1.1 Inherent instructions All inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 62. Inherent instructions Inherent instruction NOP TRAP WFI HALT RET IRET ...
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ST7232Axx-Auto 11.1.3 Direct instructions In direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub-modes: ● Direct instructions (short) The address is a byte, thus requires only one byte after the opcode, ...
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Instruction set 11.1.6 Indirect indexed instructions (short, long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X ...
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ST7232Axx-Auto 11.1.7 Relative mode instructions (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. Table 66. Relative mode instructions (direct and indirect) Available relative direct/indirect instructions JRxx CALLR ...
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Instruction set 11.3 Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the ...
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ST7232Axx-Auto Table 68. Instruction set overview Mnemo Description ADC Add with carry ADD Addition AND Logical And BCP Bit compare A, memory BRES Bit reset BSET Bit set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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Instruction set Table 68. Instruction set overview (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No operation OR OR operation ...
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ST7232Axx-Auto 12 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical characteristics 12.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 59. Pin input voltage 12.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage ...
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ST7232Axx-Auto 12.2.2 Current characteristics Table 70. Current characteristics Symbol Total current into V I VDD (source Total current out VSS (sink) Output current sunk by any standard I/O and control pin I Output current sunk by any ...
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Electrical characteristics 12.3 Operating conditions Table 72. General operating conditions Symbol f Internal clock frequency CPU Operating voltage (except Flash write/erase Operating voltage for Flash write/erase T Ambient temperature range A Figure 60. f CPU Functionality not guaranteed ...
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ST7232Axx-Auto 12.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must ...
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Electrical characteristics Power consumption vs f Figure 61. Typical I Figure 62. Typical I 158/201 : Flash devices CPU in run mode Vdd (V) in slow mode DD 1.2 1 0.8 0.6 ...
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ST7232Axx-Auto Figure 63. Typical I Figure 64. Typ. I 12.4.2 Supply and clock managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get ...
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Electrical characteristics 12.4.3 On-chip peripherals Table 75. On-chip peripherals Symbol I 16-bit timer supply current DD(TIM) I SPI supply current DD(SPI) I SCI supply current DD(SCI) I ADC supply current when converting DD(ADC) 1. Data based on a differential I ...
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ST7232Axx-Auto 12.5.2 External clock source Table 77. External clock source Symbol V OSC1 input pin high level voltage OSC1H V OSC1 input pin low level voltage OSC1L t w(OSC1H) OSC1 high or low time t w(OSC1L) t r(OSC1) OSC1 rise ...
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Electrical characteristics 12.5.3 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the ...
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ST7232Axx-Auto Table 79. Examples of typical resonators (1) Oscil. Reference LP CSA2.00MG MP CSA4.00MG MS CSA8.00MTZ CSA16.00MXZ040 HS (4) 1. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external components and to verify oscillator ...
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Electrical characteristics 12.6 Memory characteristics 12.6.1 RAM and hardware registers Table 81. RAM and hardware registers Symbol V Data retention mode RM 1. Minimum V supply voltage without losing data stored in RAM (in halt mode or under reset) or ...
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ST7232Axx-Auto 12.7 Electromagnetic compatability (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional electromagnetic susceptibility (EMS) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
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Electrical characteristics Table 83. Electromagnetic test results Symbol Voltage limits to be applied on V any I/O pin to induce a FESD functional disturbance Fast transient voltage burst limits to be applied through V FFTB 100pF on V induce a ...
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ST7232Axx-Auto 12.7.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electro-static discharge (ESD) Electro-static discharges (a ...
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Electrical characteristics 12.8 I/O port pin characteristics 12.8.1 General characteristics Subject to general operating conditions for V Table 87. I/O general port pin characteristics Symbol Parameter Input low level voltage V IL (standard voltage devices) V Input high level voltage ...
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ST7232Axx-Auto Figure 68. Unused I/O pins configured as input 1. I/O can be left unconnected configured as output ( the software. This has the advantage of greater EMC robustness and lower cost. Figure 69. ...
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Electrical characteristics 12.8.2 Output driving current Subject to general operating conditions for V Table 88. Output driving current Symbol Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see ( ...
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ST7232Axx-Auto Figure 71. Typ. V Figure 72. Typical V Figure 73. Typical V 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0 (high-sink ports 0.9 0.8 0.7 0.6 0.5 ...
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Electrical characteristics Figure 74. Typical Ta= 14 0°C Ta=9 5° Ta=2 5°C Ta=-45 ° 2.5 3 Figure 75. Typical V 5.5 5 4.5 4 3.5 ...
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ST7232Axx-Auto 12.9 Control pin characteristics 12.9.1 Asynchronous RESET pin Subject to general operating conditions for V Table 89. Asynchronous RESET pin Symbol Parameter V Schmitt trigger voltage hysteresis hys V Input low level voltage IL V Input high level voltage ...
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Electrical characteristics 12.9.2 ICCSEL/V pin PP Subject to general operating conditions for V Table 90. ICCSEL/V Symbol V Input low level voltage IL V Input high level voltage IH I Input leakage current lkg 1. Data based on design simulation ...
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ST7232Axx-Auto 12.11 Communication interface characteristics 12.11.1 SPI (serial peripheral interface) Subject to general operating conditions for V Data based on design simulation and/or characterisation results, not tested in production. When no communication is on-going the data output line of the ...
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Electrical characteristics Figure 78. SPI slave timing diagram with CPHA = 0 SS INPUT t su(SS) CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 t (SO) a MISO see note 2 OUTPUT t su(SI) MOSI INPUT ...
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ST7232Axx-Auto Figure 80. SPI master timing diagram SS INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA=1 CPOL=0 CPHA = 1 CPOL = 1 MISO INPUT MOSI see note 2 OUTPUT 1. Measurement points are ...
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Electrical characteristics 12.12 10-bit ADC characteristics Subject to general operating conditions for V Table 93. 10-bit ADC characteristics Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN I Input leakage current for ...
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ST7232Axx-Auto Figure 82. Recommended C 1. This graph shows that depending on the input signal variation (f time and decreased to allow the use of a larger serial resistor (R Figure 83. Typical A/D converter application R AIN V AIN ...
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Electrical characteristics 12.12.2 General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. ● Use separate ...
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ST7232Axx-Auto 12.12.3 ADC accuracy Table 94. ADC accuracy with V Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L 1. ...
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Package characteristics 13 Package characteristics 13.1 Package mechanical data Figure 86. 32-pin LQFP outline Table 95. 32-pin LQFP mechanical data Dim 0.050 A2 1.350 b 0.300 C 0.090 θ L 0.450 L1 182/201 ...
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ST7232Axx-Auto Figure 87. 44-pin LQFP outline Table 96. 44-pin LQFP mechanical data Dim 0.050 A2 1.350 b 0.300 C 0.090 θ L 0.450 Min Typ Max 1.600 0.150 1.400 ...
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Package characteristics 13.2 Thermal characteristics Table 97. Thermal characteristics Symbol Package thermal resistance (junction to ambient) R LQFP32 thJA LQFP44 P Power dissipation D T Maximum junction temperature Jmax 1. The maximum power dissipation is obtained from the formula P ...
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ST7232Axx-Auto 14 Device configuration and ordering information 14.1 Introduction Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST7232A-Auto are ROM versions. ST72P32A-Auto devices are factory advanced service technique ROM ...
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Device configuration and ordering information Table 100. Option byte 0 description Bit Bit name Watchdog reset on halt This option bit determines if a reset is generated when entering halt mode while the 7 WDG HALT watchdog is active. 0: ...
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ST7232Axx-Auto Table 101. Option byte 1 description (continued) Bit Bit name Oscillator range When the resonator oscillator is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. Otherwise, these bits ...
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... E = Lead-free (ECOPACK®) Conditioning options R = Tape and reel (left blank if tray -40 to +85° -40 to +125° Low profile quad flat pack Kbytes Kbytes pins pins ST72F32A serve as guides for ordering. The STMicroelectronics ST7232Axx-Auto to and Table 105: ROM factory ...
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... The two characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. ‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and program memory size. ...
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... The two characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. ‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and program memory size. ...
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... ST7232Axx-Auto Customer: ..................................................................... Address: ..................................................................... ..................................................................... Contact: ..................................................................... Phone No: ..................................................................... Reference/ROM or FASTROM code: ............................... The FASTROM/ROM code name is assigned by STMicroelectronics. FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ---------------------------------------------------------------------------------------------------------------------------------------------- ROM ---------------------------------------------------------------------------------------------------------------------------------------------- LQFP32: LQFP44: ---------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------- FASTROM ---------------------------------------------------------------------------------------------------------------------------------------------- LQFP32: LQFP44: ---------------------------------------------------------------------------------------------------------------------------------------------- Conditioning (check only one option): ...
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... The cosmic C compiler is available in a free version that outputs Kbytes of code. The range of hardware tools includes cost effective ST7-DVP3 series emulators. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface. ...
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... ST7232Axx-Auto Table 106. STMicroelectronics development tools Supported products ST7232AJ, ST7MDT20- ST72F32AJ ST7232AK, ST7MDT20- ST72F32AK 1. Add suffix /EU, /UK, /US for the power supply of your region. 14.4.5 Socket and emulator adapter information For information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in ...
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Known limitations 15 Known limitations 15.1 All Flash and ROM devices 15.1.1 Safe connection of OSC1/OSC2 pins The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main oscillator may start and, in this configuration, could generate ...
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ST7232Axx-Auto Case 1: Writing to PxOR or PxDDR with global interrupts enabled: LD A,#01 LD sema,A; set the semaphore to '1' LD A,PFDR AND A,#02 LD X,A; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; Write ...
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Known limitations RIM ; reset the interrupt mask LD A,sema ; check the semaphore status CP A,#$01 jrne OUT call call_routine ; call the interrupt routine RIM OUT:RIM JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH ...
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ST7232Axx-Auto Nested interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: ● The interrupt flag is cleared within its own interrupt routine ● The interrupt flag is cleared within any interrupt routine with higher ...
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Known limitations 15.1.7 SCI wrong break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected ...
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ST7232Axx-Auto 15.2 ROM devices only 15.2.1 I/O port A and F configuration When using an external quartz crystal or ceramic resonator, a few f be lost when the signal pattern in device to enter test mode and return to user ...
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Revision history 16 Revision history Table 109. Document revision history Date Revision 28-Jan-2008 200/201 1 Initial release ST7232Axx-Auto Changes ...