ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 87

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Note:
1
2
3
4
5
6
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see
Figure 41 on page 88
PWM mode.
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OC
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
In Flash devices, the TAOC2HR, TAOC2LR registers are ‘write only’ in Timer A. The
corresponding event cannot be generated (OCF2 is forced by hardware to 0).
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
Figure 39. Output compare block diagram
16-bit
16 bit free running counter
OC1R register
Output compare circuit
16-bit
OC2R register
16-bit
for an example with f
i
R register and the OLVi bit should be changed after each
OC1E
OCIE
OC2E
OCF1
Figure 40 on page 88
CPU
FOLV2 FOLV1
/4). This behavior is the same in OPM or
OCF2
CC1
CR1 (control register 1)
OLVL2
CC0
SR (status register)
0
for an example with f
0
CR2 (control register 2)
OLVL1
0
On-chip peripherals
Latch
Latch
1
2
CPU
/2 and
OCMP2
OCMP1
87/201
pin
pin