ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 115

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Control/status register (SPICSR)
Table 42.
SPICSR
SPIF
Bit
R
7
7
6
5
4
3
2
SPICSR register description
WCOL
Bit name
R
WCOL
MODF
6
SPIF
OVR
SOD
-
OVR
Serial peripheral data transfer flag
Write collision status
SPI overrun error
Mode fault flag
Reserved, must be kept cleared.
SPI output disable
R
5
This bit is set by hardware when a transfer has been completed. An
interrupt is generated if SPIE = 1 in the SPICR register. It is cleared
by a software sequence (an access to the SPICSR register followed
by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been
completed
Note: While the SPIF bit is set, all writes to the SPIDR register are
inhibited until the SPICSR register is read.
This bit is set by hardware when a write to the SPIDR register is
done during a transmit sequence. It is cleared by a software
sequence (see
0: No write collision occurred
1: A write collision has been detected
This bit is set by hardware when the byte currently being received in
the shift register is ready to be transferred into the SPIDR register
while SPIF = 1 (see
interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master
mode (see
interrupt can be generated if SPIE = 1 in the SPICSR register. This
bit is cleared by a software sequence (an access to the SPICR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI output (MOSI in master mode/MISO in
slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
MODF
R
4
Master mode fault (MODF) on page
Figure
Overrun condition (OVR) on page
R/W
51).
3
-
Function
SOD
R/W
2
Reset value: 0000 0000 (00h)
On-chip peripherals
110). An SPI
SSM
R/W
1
110). An
R/W
SSI
115/201
0