ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 186

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

Device configuration and ordering information
Table 100. Option byte 0 description
Table 101. Option byte 1 description
186/201
5:1
Bit
Bit
5:4
7
6
0
7
6
OSCTYPE[1:0]
WDG HALT
WDG SW
Bit name
Bit name
FMP_R
RSTC
PKG1
-
Watchdog reset on halt
Hardware or software watchdog
Reserved, must be kept at default value
Flash memory read-out protection
Pin package selection bit
Reset clock cycle selection
Oscillator type
This option bit determines if a reset is generated when entering halt mode while the
watchdog is active.
0: No reset generation when entering halt mode
1: Reset generation when entering halt mode
This option bit selects the watchdog type
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Read-out protection, when selected, provides a protection against program
memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option is selected causes the whole
user memory to be erased first, and the device can be reprogrammed. Refer to
Section 4.3.1: Read-out protection on page 28
reference manual for more details.
0: Read-out protection enabled
1: Read-out protection disabled
This option bit selects the package (see
Note: On the chip, each I/O port has 8 pads. Pads that are not bonded to external
pins are in input pull-up configuration after reset. The configuration of these pads
must be kept at reset state to avoid added current consumption.
This option bit selects the number of CPU cycles applied during the reset phase
and when exiting halt mode. For resonator oscillators, it is advised to select 4096
due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
These option bits select the ST7 main clock source type:
00: Clock source = Resonator oscillator
01: Reserved
10: Reserved
11: Clock source = External source
Function
Function
Table
102)
and the ST7 Flash programming
ST7232Axx-Auto