ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 111

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Note:
Figure 51. Clearing the WCOL bit (write collision flag) software sequence
1.
Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports are forced to be
inputs at that time, thus disabling the slave devices.
To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master receives the previous byte back from the slave device if all MISO and MOSI
pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Writing to the SPIDR register instead of reading it does not reset the WCOL bits.
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st step
2nd step
Figure
Read SPICSR
Read SPIDR
52).
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st step
2nd step
WCOL = 0
SPIF = 0
Result
Read SPICSR
Read SPIDR
WCOL = 0
Result
On-chip peripherals
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