FAN9611 Fairchild Semiconductor, FAN9611 Datasheet - Page 25

• Manufacturer Part Number: FAN9611
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN9611 / FAN9612 • Rev. 1.1.4
R
C
C
C
C
Step 12: Soft-Start Capacitor
where 5μA is the charge current of the soft-start
capacitor and 0.3
current charging the output capacitor of the converter
during the soft-start process. It is imperative to limit the
charge current of the output capacitor to be able to
maintain closed-loop soft-start of the converter. The 0.3
factor used in the C
voltage at the end of the soft-start period and provides
sufficient margin to supply current to the load while the
output capacitor is charging.
Step 13: Compensation Components
where 4.1V is the control range of the error amplifier
and f
is important to consider that the lowest output ripple
frequency limits the voltage loop crossover frequency. In
PFC applications, that frequency is two times the AC
line frequency. Therefore, the voltage loop bandwidth
(f
To guarantee closed-loop soft-start operation under all
conditions, it is recommended that:
This relationship is determined by the ratio between the
maximum output current of the g
maximum charge current of the soft-start capacitor.
Observing this correlation between the two capacitor
values ensures that the compensation capacitor voltage
can be adjusted faster than any voltage change taking
place across the soft-start capacitor. Therefore, during
startup the voltage regulation loop’s response to the
increasing soft-start voltage is not limited by the finite
current capability of the error amplifier.
where f
error amplifier compensation network against high-
frequency noise in the feedback loop. The pole should
be placed at least a decade higher than f
it does not interfere with the phase margin of the voltage
regulation loop at its crossover frequency. It should also
be sufficiently lower then the switching frequency of the
SS
0
COMP,
COMP,
COMP
COMP,
), is typically in the 5Hz to 15Hz range.

0
LF
is the desired voltage loop crossover frequency. It
HF
5
HF

HFP
μA


2

0.3
is the frequency of a pole implemented in the
4.1V


4
2
C
π



OUT
I
C
OUT,

π
f
SS

0
g

C

M
1

f
MAX
HFP

C
·
OUT
R
SS

I
1
OUT,MAX
I
COMP,
FB1
OUT,
equation can prevent output over



R
R


2
MAX
COMP
FB2
LF
R

π
FB2
is the maximum output

f
0


M
2
error amplifier to the

R
FB1
R
0

FB2
to ensure that
R
FB2
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(21)
(22)
(23)
25
R
R
R
R
R
converter so noise can be effectively attenuated. The
recommended f
applications.
Step 14: Over-Voltage Protection Setting
(OVP)
where 3.5V is the threshold voltage of the OVP
comparator and P
resistive divider network. Typical P
the 50mW to 100mW range.
R
two or three resistors; depending on safety regulations,
maximum voltage, and or power rating of the selected
resistor type.
Step 15: Input Line Voltage Sense
Resistors
where 0.925V is the brown-out protection threshold at
the VIN pin. V
operating voltage. Its divided down level at the VIN pin
corresponds to the 0.925V brown out protection
threshold. V
anticipated in the design and P
dissipation of the R
voltage equals V
the 50mW to 100mW range.
R
or three resistors; depending on safety regulations,
maximum voltage, and or power rating of the selected
resistor type.
where 0.925V is the threshold voltage of the line under-
voltage lockout comparator and 2μA is the sink current
provided at the VIN pin during line under-voltage
(brownout) condition. The sink current, together with the
terminating impedance of the VIN pin determines the
hysteresis between the turn-on and turn-off thresholds.
OV2
OV1
IN
IN1
INHYST
OV1
IN1
2
can be implemented as a series combination of two




can be implemented as a series combination of








3.5V
. 0

V
2
OUT,
925
2

0.925V




3.5V
V
LINE,MAX


V
V
P
LINE
V
LATCH
2
OUT,
OVP
LINE,
HFP

R

LINE,MAX
LINE,MIN
V
,
V
MIN
IN1
MIN
LATCH
OVP
LINE,
2
frequency is around 120Hz in PFC
is the maximum input RMS voltage
LINE

IN1


1

P

  

ON
R
. Typical P
is the total dissipation of the
INSNS
1
,
- R
MAX
is the minimum input RMS
2
R
IN2





μA
OV2

R
R
IN2
IN2
IN2
divider when the input
INSNS

INSNS
. 0
OVP
925
is the total power
power loss is in
power loss is in
V
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



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