FAN5355 Fairchild Semiconductor, FAN5355 Datasheet - Page 19

• Manufacturer Part Number: FAN5355
• Description: The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.0
Switching-Frequency Control and
Synchronization
The nominal internal oscillator frequency is 3MHz. The
regulator runs at its internal clock frequency until these
conditions are met:
1.
2.
Table 5. SYNC Frequency Validation for f
If the EN_SYNC is set and SYNC fails validation, the regulator
continues to run at its internal oscillator frequency. The
regulator is functional if f
but its performance is compromised if f
window in the Electrical Specifications.
When CONTROL1[3:2] = 00 and the VSEL line is LOW, the
converter
CONTROL1[0], with synchronization disabled regardless of
the state of the EN_SYNC and HW_nSW bits.
Output Voltage Transitions
The IC regulates V
determined by the VSEL pin and the HW_nSW bit.
Table 6. V
CONTROL1[3:2] = 00
If HW_nSW = 0, V
following sequence:
1.
2.
If HW_nSW = 1, V
changing the state of the VSEL pin or by writing to the VSEL
register selected by the VSEL pin.
Positive Transitions
When transitioning to a higher V
the transition using multi-step or single-step mode.
VSEL Pin
PLL_MULT
EN_SYNC bit, CONTROL1[5], is set; and
A valid frequency appears on the SYNC pin.
Write the new setpoint in VSEL1.
Write desired transition rate in DEFSLEW,
CONTROL2[2:0], and set the GO bit in CONTROL2[7].
0
1
x
00
01
10
11
CONTROL2
OUT
operates
HW_nSW Bit
Set Point and Mode Control MODE_CTRL,
f
SYNC
OUT
1
1
0
OUT
Divider
1
2
3
4
OUT
according
to one of two set point voltages, as
transitions are initiated through the
SYNC
transitions are initiated either by
is valid, as defined in Table 5,
V
OUT
OUT
Min.
1.80
0.90
0.60
0.45
, the regulator can perform
VSEL0
VSEL1
VSEL1
to
Set Point
SYNC
f
OSC(INTERNAL)
SYNC
the
Typ.
3.00
1.50
1.00
0.75
is outside the f
Valid
MODE0
Per MODE1
Per MODE1
=3.0MHz
Allowed
Max.
4.00
2.00
1.33
1.00
PFM
SYNC
bit,
19
Multi-Step Mode:
Applies to Options 03 and 06 only.
The internal DAC is stepped at a rate defined by DEFSLEW,
CONTROL2[2:0], ranging from 000 to 110. This mode
minimizes the current required to charge C
minimizes
transitioning. The PWROK bit, CONTROL2[5], remains LOW
until about 1.5s after the DAC completes its ramp.
Single-Step Mode:
Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC
is immediately set to the higher voltage and the regulator
performs the transition as quickly as its current-limit circuit
allows, while avoiding excessive overshoot.
Figure 39 shows single-step transition timing. t
it takes the regulator to settle to within 2% of the new set point
and is typically 7s for a full-range transition (from 000000 to
111111). The PWROK bit, CONTROL2[5], goes LOW until the
transition is complete and V
~2s after t
It is good practice to reduce the load current before making
positive VSEL transitions. This reduces the time required to
make positive load transitions and avoids current-limit-induced
overshoot.
All positive V
complete, which occurs at the end of t
PWROK
VOUT
VSEL
PWROK
VOUT
VSEL
Figure 39. Single-Step V
Figure 38. Multi-Step V
V(L-H)
the
OUT
.
transitions inhibit PFM until the transition is
current
VHIGH
VHIGH
drain
OUT
settled. This typically occurs
VLOW
t
t
from
V(L-H)
POK(L-H)
OUT
t
POK(L-H)
OUT
VLOW
POK(L-H)
Transition
Transition
the
.
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OUT
98% VHIGH
V(L-H)
battery
and thereby
is the time
when