FAN5355 Fairchild Semiconductor, FAN5355 Datasheet - Page 21

• Manufacturer Part Number: FAN5355
• Description: The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.0
A transaction ends with a “STOP” condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 43.
During a read from the FAN5355 (Figure 46), the master
issues a “Repeated Start” after sending the register address
and before resending the slave address. The “Repeated Start”
is a 1 to 0 transition on SDA while SCL is HIGH, as shown in
Figure 44.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in FS mode (less than
400KHz clock) and slaves do not ACK this transmission.
SDA
SCL
SDA
SCL
S
T
Slave Address
HD;STA
ACK(0) or
NACK(1)
Figure 42. Start Bit
Slave Releases
Figure 43. Stop Bit
7 bits
S
Slave Address
0
Master Drives
Slave Address
7 bits
A
0
MS Bit
Reg Addr
8 bits
t
HD;STO
0
Figure 45. Write Transaction
Figure 46. Read Transaction
A
0
Reg Addr
A
0
8 bits
21
R
The master then generates a repeated-start condition (Figure
44) that causes all slaves on the bus to switch to HS mode.
The master then sends I
using the HS-mode clock rate and timing.
The bus remains in HS mode until a stop bit (Figure 43) is
sent by the master. While in HS mode, packets are separated
by repeated-start conditions (Figure 44).
Read and Write Transactions
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
defined as
All addresses and data are MSB first.
Table 9.
Symbol Definition
Slave Address
SDA
SCL
S
A
R
P
A
7 bits
A
0
I
START, see Figure 42.
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
NACK. The slave sends a 1 to NACK the
preceding packet.
Repeated START, see Figure 44.
STOP, see Figure 43.
2
Figure 44. Repeated-Start Timing
C Bit Definitions for Figure 45 - Figure 46
Master Drives Bus
8 bits
ACK(0) or
Slave Releases
NACK(1)
Data
1
0
A
2
C packets, as described above,
A
0
8 bits
Data
P
and
t
SU;STA
Slave Drives Bus
t
HD;STA
1
A
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P
SLADDR
MS Bit
.