FAN5404 Fairchild Semiconductor, FAN5404 Datasheet
FAN5404
Available stocks
Related parts for FAN5404
FAN5404 Summary of contents
Page 1
... FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator Features Fully Integrated, High-Efficiency Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs Faster Charging than Linear 0.5% at 25°C Charge Voltage Accuracy: 1% from 0 to 125°C ...
Page 2
... PN Bits: Number Address REG3[4:3] FAN5400 01 1101011 FAN5401 00 1101011 FAN5402 01 1101011 FAN5403 10 1101011 FAN5404 11 1101011 FAN5405 10 1101010 Note: 1. Special charger is a current limited charger that is not a USB compliant source. Table 2. Recommended External Components Component Description L1 1H, 20%, 1.3A, 2016 C 10F, 20%, 6.3V, X5R, 0603 ...
Page 3
... Block Diagram VBUS C IN1 PMID Q1A Greater than VBAT ON Less than VBAT OFF © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Figure 2. IC and System Block Diagram PMID Q3 CHARGE PUMP Q1 Q1A CSIN Q1B SW Q1B Q2 OFF ON PGND VBAT SYSTEM Figure 3. Power Stage ...
Page 4
... Mode. Bypass with a 1F capacitor to PGND. FAN5402 FAN5403, Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is E2 DISABLE FAN5404, controlled by the I FAN5405 does not affect the 32-second timer. Regulator Output. Connect to a 1F capacitor to PGND. This pin can supply up to 2mA of E3 ...
Page 5
... T J(max) Symbol Parameter Junction-to-Ambient Thermal Resistance JA Junction-to-PCB Thermal Resistance JB © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Parameter Continuous Pulsed, 100ms Maximum Non-Repetitive Human Body Model per JESD22-A114 Charged Device Model per JESD22-C101 Parameter T < ...
Page 6
... Input Bias Current IN Charge Termination Detection Termination Current Range I (TERM) Termination Current Accuracy Termination Current Deglitch Time 1.8V Linear Regulator V 1.8V Regulator Output REG © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Conditions V > PWM Switching BUS BUS(min) V > PWM Enabled, BUS ...
Page 7
... Oscillator Frequency SW D Maximum Duty Cycle MAX D Minimum Duty Cycle MIN Synchronous to Non-Synchronous I SYNC Current Cut-Off Threshold © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Conditions To Initiate and Pass VBUS Validation During Charging I Set to 100mA IN I Set to 500mA IN V > > ...
Page 8
... Rising BAT V Falling BAT V < V BAT SHORT (6) T Rising J T Falling J (6) Charge Current Reduction Begins Charger Enabled Charger Disabled 15-Minute Mode (FAN5400, FAN5402, FAN5404, FAN5405) Charger Inactive (discharging the battery). BUS . SYNC 8 and =25°C. J Min. Typ. Max. Units 4.80 5.07 5. ...
Page 9
... SCL Fall Time FCL SDA Rise Time t Rise Time of SCL after a RDA Repeated START Condition t RCL1 and after ACK Bit © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Conditions Standard Mode Fast Mode High-Speed Mode, C < 100pF B High-Speed Mode, C < 400pF ...
Page 10
... REPEATED START = MCS Current Source Pull- Resistor Pull-up P Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. Figure 6. I © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Conditions Standard Mode Fast Mode High-Speed Mode, C < 100pF B High-Speed Mode, C < ...
Page 11
... V BAT Load Current (mA) Figure 9. Charger Efficiency Figure 11. Auto-Charge Startup =100mA, OTG=1, V INLIM © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =4.2V, V =5.0V, and T OREG BUS 900 800 700 600 500 400 300 200 100 4 4 ...
Page 12
... Figure 13. AutoCharge Startup with 300mA Limited Charger / Adaptor, I =500mA, OTG=1, V INLIM Figure 15. Battery Removal / Insertion during Charging, V =3.9V, I =950mA BAT OCHARGE © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =4.2V, V =5.0V, and T =25°C. OREG BUS A Figure 14. Charger Startup with HZ_MODE Bit Reset, =3.4V ...
Page 13
... Power-up; FAN5400, FAN5403 Figure 18. No Battery at V BUS 200 150 -30C +25C +85C 100 50 0 4.0 4.5 5.0 Input Voltage, V BUS Figure 19. VBUS Current in High-Impedance Mode with Battery Open © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =4.2V, V =5.0V, and T OREG BUS 1.82 1.81 1.80 1.79 1.78 1.77 5.5 6.0 0 (V) 13 =25°C. ...
Page 14
... V Load Current (mA) BUS Figure 23. Output Regulation vs. V 250 200 150 100 50 2 2.5 3 3.5 Battery Voltage, V Figure 25. Quiescent Current © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =3.6V, T =25°C. BAT A 100 2.7VBAT 80 3.6VBAT 4.2VBAT 75 200 250 300 0 BAT 5 ...
Page 15
... Unless otherwise specified, using circuit of Figure 1, V Figure 27. Boost PWM Waveform 100 150 V Load Current (mA) BUS Figure 29. Output Ripple vs. V © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =3.6V, T =25°C. BAT A Figure 28. Boost PFM Waveform 30 2.7VBAT 3.6VBAT 25 4.2VBAT 4.5VBAT ...
Page 16
... Boost Mode Typical Characteristics Unless otherwise specified, using circuit of Figure 1, V Figure 31. Startup, 3.6V , 44 Load, Additional 10µF, BAT X5R Across V Figure 33. Load Transient, 5-155-5mA, t © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 =3.6V, T =25°C. BAT A Figure 32. V BUS =t =100ns Figure 34. Load Transient, 5-255-5mA, t ...
Page 17
... V reaches V BAT charging circuit is then started and the battery is charged © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. The FAN540X is designed to work with a current-limited input source at VBUS ...
Page 18
... Output Voltage Regulation Battery Charging Current Limit Input Current Limit Charge Termination Limit Weak Battery Voltage © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 A new charge cycle begins when one of the following occurs: OUT The battery voltage falls below V ...
Page 19
... Table 7. Input Current Limit and below VBUS for OVP I INLIM For all versions except the FAN5401 and FAN5404, the OTG pin establishes the input current limit when t For the FAN5401 and FAN5404, no charging occurs automatically at VBUS POR, so the input current limit is established by the I 19 ...
Page 20
... Flow Charts © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Figure 37. Charger VBUS POR 20 www.fairchildsemi.com ...
Page 21
... Indicate Charging NO Disable Charging Timeout? Indicate VBUS Fault I OUT NO Termination enabled V BAT Stop Charging Enable IDET for T © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Disable Charging Indicate VBUS Fault Enable I , SHORT Reset Safety reg Indicate Charging T 15MIN YES NO HIGHZ mode < ...
Page 22
... Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Figure 39. Charge Configuration Figure 40. HZ-State 22 www.fairchildsemi.com ...
Page 23
... Charge Start Start T 15MIN T 15MIN Active? Figure 41. Timer Flow Chart for FAN5400, FAN5402, FAN5403, FAN5405 Reset T 32SEC YES Figure 42. Timer Flow Chart for FAN5401, FAN5404 © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Reset Registers NO Start T 32SEC YES Stop T 15MIN ...
Page 24
... Special Charger FAN5403-05 Only The FAN5403, FAN5404, and FAN5405 have additional functionality to limit input current in case a current-limited “special charger” is supplying VBUS. The FAN5403-05 slowly increases the charging current until either: reached INLIM OCHARGE or BUS ...
Page 25
... OREG no further pulses occur for 30ms, the IC sets the FAULT bits to 100, sets the STAT bits to 11, and pulses the STAT pin. © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Battery Detection During Charging The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set ...
Page 26
... Thermal Shutdown Timer Fault Battery © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Charge Mode Control Bits Setting either HZ_MODE or CE through I is set to No Limit. charger and puts the IC into High-Impedance Mode and resets t 32S t begins running and, when it overflows, all registers ...
Page 27
... Figure 33 and Figure 43. 350 325 300 275 250 225 200 2.0 2.5 3.0 3.5 Battery Voltage, V BAT Figure 43. Output Resistance (R © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0 function of I BUS regulator is in PWM Mode (continuous conduction) as: V OUT At V =3.3V, and I BAT V OUT At V =2.7V, and I ...
Page 28
... CURRENT 0 64 BOOST ENABLED Figure 44. Boost Response Attempting to Start into V Short Circuit (Times in s) © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 VREG Pin The VREG pin on FAN5400 - FAN5402 provides a voltage modulation protected from over-voltage surges on VBUS, which can be ON used to run auxiliary circuits ...
Page 29
... Charging Current Controlled by 3 ICHG I Control Loop CHARGE 2 IBUS I Limiting Charging Current BUS 1 VBUS_VALID V Not Valid BUS 0 CV Constant Current Charging © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 STATE 0 < – V ITERM CSIN BAT < 1mV V – V CSIN BAT V > V BAT SHORT V > ...
Page 30
... The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. Slave Address 2 Table 20 Slave Address Byte Part Types FAN5400–FAN5404 FAN5405 hex notation, the slave address assumes a 0 LSB. The hex slave address for the FAN5405 is D4H and is D6H for all other parts in the family ...
Page 31
... Bus control is signified by the shading of the packet, Master Drives Bus defined as and All addresses and data 7 bits S Slave Address 7 bits S Slave Address 0 © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Table 21. Bit Definitions for Figure 49, Figure 50 Symbol Slave Drives Bus . S are MSB first bits ...
Page 32
... Name Value Type CONTROL0 TMR_RST 7 1 OTG 0 R/W 6 EN_STAT 5:4 STAT BOOST 1 2:0 FAULT © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 Register Name REG# CONTROL0 0 CONTROL1 1 OREG 2 03 IC_INFO or 3BH IBAT 4 SP_CHARGER 5 SAFETY 6 MONITOR 10H Register Address Writing a 1 resets the t timer ...
Page 33
... OTG pin active LOW OTG pin active HIGH Disables OTG pin Enables OTG pin Register Address Identifies Fairchild Semiconductor as the IC supplier R Part number bits, see the Ordering Info on page Revision, revision 1.X, where X is the decimal of these three bits Register Address: 04 ...
Page 34
... T_120 See 3 ICHG Table 19 2 IBUS 1 VBUS_VALID 0 CV © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 (Continued) Register Address Unused 1.8V regulator is ON 1.8V regulator is OFF Output current is controlled by IOCHARGE bits Voltage across R for output current control is set to 22.1mV (325mA for ...
Page 35
... In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. All power and ground pins must be © 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 routed to their bypass capacitors using top copper if possible ...
Page 36
... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
Page 37
... Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 37 www.fairchildsemi.com ...