74LCX125MTC Fairchild Semiconductor, 74LCX125MTC Datasheet

IC BUFFER QUAD LV N-INV 14TSSOP

74LCX125MTC

Manufacturer Part Number
74LCX125MTC
Description
IC BUFFER QUAD LV N-INV 14TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX125MTC

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Logic Family
74LCX
Number Of Channels Per Chip
Quad
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
85 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Input Bias Current (max)
10 uA
Low Level Output Current
24 mA
Maximum Power Dissipation
25 pF
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
6.5 ns @ 2.7 V or 6 ns @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Logic Device Type
Buffer, Non Inverting
Supply Voltage Range
2V To 3.6V
Logic Case Style
TSSOP
No. Of Pins
14
Operating Temperature Range
-40°C To +85°C
Family Type
LCX
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX125MTC
Manufacturer:
FAIRCHILD
Quantity:
20 000
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Manufacturer:
Fairchil
Quantity:
5 000
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Manufacturer:
SAMSUNG
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Part Number:
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Company:
Part Number:
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©1995 Fairchild Semiconductor Corporation
74LCX125 Rev. 1.7.0
74LCX125
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
Note:
1. To ensure the high-impedance state during power up
Ordering Information
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LCX125M
74LCX125SJ
74LCX125BQX
74LCX125MTC
Order Number
5V tolerant inputs and outputs
2.3V–3.6V V
6.0ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
– Machine model
Leadless DQFN package
or down, OE should be tied to V
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
All packages are lead free per JEDEC: J-STD-020B standard.
PD
max. (V
CC
(2)
specifications provided
CC
Package
Number
100V
MLP14A
MTC14
M14A
M14D
CC
3.3V), 10µA I
2000V
3.0V)
CC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
(1)
through a pull-up
CC
max.
General Description
The LCX125 contains four independent non-inverting
buffers with 3-STATE outputs. The inputs tolerate volt-
ages up to 7V allowing the interface of 5V systems to 3V
systems.
The 74LCX125 is fabricated with an advanced CMOS
technology to achieve high speed operation while main-
taining CMOS low power dissipation.
Package Description
February 2008
www.fairchildsemi.com

Related parts for 74LCX125MTC

74LCX125MTC Summary of contents

Page 1

... M14A 74LCX125SJ M14D (2) 74LCX125BQX MLP14A 74LCX125MTC MTC14 Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev ...

Page 2

... Pin Assignments for SOIC, SOP, and TSSOP (Top View) Pad Assignments for DQFN (Top Through View) Pin Description Pin Names Description A Inputs n OE Output Enable Inputs n O Outputs n ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 Logic Symbol IEEE/IEC Truth Table Inputs ...

Page 3

... CC V 2.7V–3. 2.3V–2. Free-Air Operating Temperature Input Edge Rate, V Note: 4. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 Parameter (3) GND I (4) Parameter 0.8V–2.0V Rating –0.5V to +7.0V –0.5V to +7.0V – ...

Page 4

... Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 V (V) Conditions CC 2.3– ...

Page 5

... Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 V (V) Conditions CC 3.3 C 50pF, V 3.3V 2.5 C 30pF, V 2.5V 3.3 C 50pF ...

Page 6

... Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics 1MHz, t ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 (Generic for LCX Family) includes probe and jig capacitance) L ...

Page 7

... Schematic Diagram (Generic for LCX Family) ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 7 www.fairchildsemi.com ...

Page 8

... BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) ©1995 Fairchild Semiconductor Corporation 74LCX125 Rev. 1.7.0 Tape Section Number of Cavities 125 (Typ.) Carrier 3000 75 (Typ 0.512 (13.00) 0.795 (20.20) ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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