ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 14

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

PFD and Loop Filters
The PFD compares the input reference with that of the
locking frequency (feedback) giving a phase error which is
then filtered by a 100Hz low pass filter, to give the
average phase error for input into a loop filter. The PFD is
quite complex and has several programmable options to
determine what phase error value is fed to the loop (See
“Phase and Frequency Detectors” on page 15.”)
depending on the type of jitter/wander expected.
The loop filter bandwidth and damping is programmable
to optimize the locking time/ability to track the input. See
Figure 5 and “Damping Factor Programmability” on
page 15.
PLL Operational Controls
The main factors controlling the operation of the PLL are:
1. Input reference and feedback frequency selection -
2. Loop Bandwidth and Damping factor of the DPLLs -
Figure 5 DPLL1 Jitter Transfer Characteristic, (Freq. = 1.544 MHz, Jitter = 0.2 UI p-p, Damping Factor = 5)
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
See “PLL Architecture” on page 11., and “Input
Locking Frequency Modes” on page 7.
these determine how fast the device can to lock to the
selected input, or how tightly it can track the input.
FINAL
Page 14
3. PFD settings - these affect the input phase error to the
DPLL1 initially tries to lock to the input frequency of the
selected input SEC. By default, it uses a wide “acquisition”
bandwidth setting until it has achieved frequency lock,
then DPLL1 switches to using a narrower “Locked”
bandwidth setting as it locks to the phase of the input.
Input Acquisition Bandwidth
DPLL1 has programmable acquisition bandwidth of 18,
35 or 70 Hz. The default is set to 70 Hz.
Input Locked Bandwidth
The ACS8526 has programmable “Locked” bandwidth of
18, 35 or 70 Hz. These bandwidth settings correspond to
the -3 dB jitter attenuation point on the ACS8526’s jitter
transfer characteristic shown in Figure 5. If the ACS8526
is used with only DPLL1, the highest bandwidth setting is
recommended to ensure the closest tracking of the input
SEC. If DPLL2 is also to be used, DPLL1 should be set to
a lower bandwidth setting than DPLL2. The lowest
bandwidth setting will provide the highest jitter
attenuation, although this is not the main function of the
ACS8526 device.
Loop filter and relate to jitter and wander tolerance -
See “Phase/Frequency/Lock Detection” on page 15.
ACS8526 LC/P LITE
DATASHEET
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