ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 5

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Table 3 Other Pins (cont...)
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
18
19,
20
28
29
30
33
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
51
52
56
63
64
Pin Number
MFrSync
O1POS,
O1NEG
IP_FREQ0
SEC1
SEC2
IP_FREQ1
IP_FREQ2
O2_FREQ0
O2_FREQ2
TRST
O2_FREQ1
TMS
CLKE
SDI
CSB
O1_FREQ0
O1_FREQ1
SCLK
PORB
TCK
TDO
TDI
SDO
O2
O1_FREQ2
SONSDHB
Symbol
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVDS/PECL
TTL/CMOS
TTL/CMOS
TTL/CMOS
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
D
D
D
D
D
D
D
D
D
D
D
D
U
U
U
D
U
D
D
D
U
D
Output Reference: 2 kHz Multi-Frame Sync output.
Output Reference 1: Differential output., default LVDS.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Input Reference 1: Primary input.
Input Reference 2: Secondary input.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Output O2 Frequency Select: Frequency select for output O2.
Output O2 Frequency Select: Frequency select for output O2.
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.
TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.
Output O2 Frequency Select: Frequency select for output O2.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.
NC if not used.
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of
SCLK to be active.
Chip Select (Active Low): This pin is asserted Low by the external device
(microprocessor) to enable the Serial interface.
Output O1 Frequency Select: Frequency select for output O1.
Output O1 Frequency Select: Frequency select for output O1.
Serial Data Clock: The Low to High transition on this input latches the data on the
SDI input into the internal registers. The active clock edge (defined by CLKE)
latches the data out of the internal registers onto the SDO output.
Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset
back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.
Interface Address: SPI compatible Serial Data Output.
Output Reference: Programmable, default 19.44 MHz.
Output O1 Frequency Select: Frequency select for output O1.
SONET or SDH frequency select: Sets the initial power-up state (or state after a
PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and
Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after
power-up by software. When set Low, SDH rates are selected (2.048 MHz etc.)
and when set High, SONET rates are selected (1.544 MHz etc.) The register
states can be changed after power-up by software.
Interface Address: SPI compatible Serial Data Input.
FINAL
Page 5
Description
ACS8526 LC/P LITE
DATASHEET
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