ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 41

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Address (hex):
Address (hex):
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:0]
Bit 7
[7:2]
[1:0]
41
42
cnfg_DPLL_freq_limit
[7:0]
Description
Bits [7:0] of cnfg_DPLL_freq_limit
This register defines the extent of frequency offset
to which DPLL1 will track a source before limiting-
i.e. it represents the pull-in range of the DPLLs. The
offset of the device is determined by the frequency
offset of the DPLL when compared to the offset of
the external crystal oscillator clocking the device. If
the oscillator is calibrated using
cnfg_nominal_frequency Reg. 3C and 3D, then this
calibration is automatically taken into account. The
DPLL frequency limit limits the offset of the DPLL
when compared to the calibrated oscillator
frequency.
cnfg_DPLL_freq_limit
[9:8]
Description
Not used.
Bits [9:8] of cnfg_DPLL_freq_limit.
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
Bits[7:0] of cnfg_DPLL_freq_limit
Bit 4
Bit 4
FINAL
Page 41
(R/W) Bits [7:0] of the DPLL
frequency limit register.
(R/W) Bits [9:8] of the DPLL
frequency limit register.
Bit Value
Bit Value
Bit 3
Bit 3
-
-
-
Value Description
In order to calculate the frequency limit in ppm,
Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need
to be concatenated. This value is a unsigned integer
and represents limit both positive and negative in
ppm. The value multiplied by 0.078 will give the
value in ppm.
Value Description
-
See Reg. 41 (cnfg_DPLL_freq_limit) for details.
Bit 2
Bit 2
ACS8526 LC/P LITE
Default Value
Default Value
Bits [9:8] of cnfg_DPLL_freq_limit
Bit 1
Bit 1
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1111 1111
0000 0011
Bit 0
Bit 0