ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 17

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

DPLL2 Main Features
DPLL2 Advanced Features
The advanced features are the same as those for DPLL1,
with DPLL2 using the configuration values for DPLL1, with
the following exceptions:
Advanced Phase Detector Controls
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Adjustable gain settings for PD2 (when enabled), for
the following feedback cases:
Always locked to DPLL1
A single programmable bandwidth control: 18*, 35 or
70 Hz
Programmable damping factor, (For optional faster
locking and peaking control) Factors = 1.2, 2.5, 5*,
10 or 20.
Digital feedback, on*/off (Reg. 35 Bit 6)
Output frequency selection (Reg. 64)
Can provide the source for the 2 kHz and 8 kHz
outputs available at Outputs 01 and 02 (Reg. 7A Bit
7).
PD2 gain control enable, on*/off (Reg. 6C Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
(Reg. 6C Bits [2:0]). If off, PD2 is not used
Adjustable gain settings for PD2 (with auto switching
enabled), for the following feedback cases:
• Digital feedback (Reg. 6D Bits [2:0])
• Analog feedback (all frequencies above 8 kHz)
• Analog 8k (or less) feedback (Reg. 6B Bits [2:0]).
• DS3/E3 support (44.736 MHz / 34.368 MHz)
• Low jitter E1/DS1 options independent of rates
• Frequencies of n x E1/DS1 including 16 and 12 x
• Squelched (clock off)
• Digital feedback (Reg. 6C Bits [2:0])
• Analog feedback (all frequencies above 8K)
• Analog 8k (or less) feedback (Reg. 6A Bits [2:0]).
(Reg. 6D Bits [6:4])
independent of rates from DPLL1
from DPLL1
E1, and 16 and 24 x DS1 supported
(Reg. 6C Bits [6:4])
FINAL
Page 17
Outputs
The ACS8526 delivers four output signals on the following
ports: Two clocks, one each on Output O1 and O2, and two
Sync signals, one each on output ports FrSync and
MFrSync. Outputs O1 and O2 are independent of each
other and are individually selectable. Output 01 is a
differential port (pins O1POS and O1NEG), and can be
selected to be PECL or LVDS via Reg. 3A
cnfg_differential_output. Output O2 (pin O2) and the Sync
outputs are TTL/CMOS compatible.
The two Sync outputs, FrSync (8 kHz) and MFrSync
(2 kHz), are derived from DPLL1.
The frequencies available on the outputs can be selected
from a range of spot frequencies by either:
Output Frequency Selection by Hardware
Tables 6 and 7 show the hardware settings for selecting
particular output frequencies on Outputs 01 and 02. Note
that the hardware frequency selection method provides
only a subset (11) of the total number of frequencies (55)
available when selecting by register programming.
Output Frequency Selection by Register
Programming
The output frequencies on O1 and O2 are controlled by a
number of interdependent parameters (refer to “PLL
Architecture” on page 11). The frequencies of the output
clocks are selectable from a range of pre-defined spot
frequencies/port technologies, as defined in Table 8.
Outputs O1 & O2 Frequency Configuration Steps
The output frequency selection is performed in the
following steps:
1. Refer to Table 10, Frequency Divider Look-up, to
2. Refer to the Table 10 to determine the required APLL
3. Refer to Table 11, APLL1 Frequencies, and Table 12,
Hardware selection: configuring the hardware pins
OP_FREQ1 [2:0], OP_FREQ2[2:0] and SONSDH, which
are read on reset, or
Register programming: writing to the registers after
the end of the initialization period.
choose a set of output frequencies.
frequency to support the frequency set.
APLL2 Frequencies, to determine in what mode
DPLL1 and DPLL2 need to be configured, considering
the output jitter level.
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