ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 27

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Local Oscillator Clock
The Master system clock on the ACS8526 should be
provided by an external clock oscillator of frequency
12.800 MHz. Wander on the local oscillator clock will not
have a significant effect on the output clock whilst in
Locked mode. In Free-Run or Holdover mode wander on
the crystal is more significant. Variation in crystal
temperature or supply voltage both cause drifts in
operating frequency, as does ageing. These effects must
be limited by careful selection of a suitable component for
the local oscillator. Please contact Semtech for
information on crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
An adjustment of ±50 ppm would be sufficient to cope
with most crystals, in fact the range is an order of
magnitude larger due to the use of two 8-bit register
locations. The setting of the cnfg_nominal_frequency
register allows for this adjustment. An increase in the
register value increases the output frequencies by
0.0196229 ppm for each LSB step.
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
range of the register is 0 to 65535 (dec), giving an adjustment
range of -771 ppm to +514 ppm of the output frequencies, in
0.0196229 ppm steps.
Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,
then the calibration value in the register to give a - 5 ppm
adjustment in output frequencies to compensate for the
crystal inaccuracy, would be:
39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).
Status Reporting
Loss of Input Signal - LOS Flag
In the event of loss of SEC input signal, LOS flag is raised
on the LOS_ALARM pin. The LOS alarm is active low, and
high impedance when inactive, i.e. when an LOS alarm
exists, the output will be driven low; with no LOS alarm,
the output will float. This is designed to be able to be
connected to a processor together with other interrupt
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 27
sources to trigger an interrupt. The output will require a
pull-up resistor to pull the voltage up when the alarm is
inactive.
Status Information
Status information can be read from the following Status
Registers:
The registers sts_current_DPLL_frequency report the
frequency of DPLL1 or DPLL2 with respect to the external
crystal XO frequency (after calibration via Reg. 3C, 3D if
used). The selection of DPLL2 or DPLL1 reporting is made
via Reg. 4B, Bit 4. The value is a 19-bit signed number
with one LSB representing 0.0003068 ppm (range of
±80 ppm). This value is actually the integral path value in
the DPLL, and as such corresponds to an averaged
measurement of the input frequency, with an averaging
time inversely proportional to the DPLL bandwidth setting.
Reading this regularly can show how the currently locked
source is varying in value e.g. due to frequency wander on
its input.
Serial Interface
The ACS8526 device has a serial interface which can be
SPI compatible.
The Motorola SPI convention is such that address and
data is transmitted and received MSB first. On the
ACS8526, device address and data are transmitted and
received LSB first. Address, read/write control and data
on the SDI pin is latched into the device on the rising edge
of the SCLK. During a read operation, serial data output
on the SDO pin can be read out of the device on either the
rising or falling edge of the SCLK depending on the logic
level of CLKE. For standard Motorola SPI compliance,
data should be clocked out of the SDO pin on the rising
edge of the SCLK so that it may be latched into the
microprocessor on the falling edge of the SCLK. Figure 7
and 8 show the timing diagrams of write and read
accesses for this interface.
The serial interface clock (SCLK) is not required to run
between accesses (i.e., when CSB = 1).
sts_current_DPLL_frequency (Reg. 0C, 0D, and 07)
sts_reference_sources (Reg. 11).
ACS8526 LC/P LITE
DATASHEET
www.semtech.com