ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 16

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

The characteristics of the loop will be similar to Lock8k
mode where again large input phase differences
contribute to the loop dynamics. Setting the bit Low only
uses a max figure of 360° in the loop and will give slower
pull-in but gives less overshoot. The final phase position
that the loop has to pull in to is still tracked and
remembered by the multi-cycle phase detector in either
case.
Phase Lock/Loss Detectors
Phase lock/loss detection is handled in several ways.
Phase loss can be triggered from:
Each of these sources of phase loss indication is
individually enabled via registers bits (see Reg. 73 and
74). Phase lock or loss is used to determine whether to
switch to nearest edge locking and whether to use
acquisition or normal bandwidth settings for the DPLL.
Acquisition bandwidth is used for faster pull-in from an
unlocked state.
The coarse phase lock detector detects phase differences
of n cycles between input and feedback clocks, where n is
set by Reg. 74, Bits [3:0]; the same register that is used
for the coarse phase detector range, since these
functions go hand in hand. This detector may be used in
the case where it is required that a phase loss indication
is not given for reasonable amounts of input jitter and so
the fine phase loss detector is disabled and the coarse
detector is used instead.
DPLL Feature Summary
(* = hardware default selection)
DPLL1 Main Features
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
The fine phase lock detector, which measures the
phase between input and feedback clock
The coarse phase lock detector, which monitors whole
cycle slips
Detection that the DPLL is at min. or max. frequency
Detection of no activity on the input.
Multiple E1 and DS1 outputs supported
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
Multiple phase loss and multiple phase detectors (see
“DPLL1 Advanced Features”)
Direct PLL locking to common SONET/SDH input
frequencies or any multiple of 8 kHz
Fast detection on input failure and entry into Digital
Holdover mode (holds at the current frequency value)
FINAL
Page 16
DPLL1 Advanced Features
Phase Loss Indicators
Phase Detector Controls
Advanced Phase Detector Controls
Frequency translation between input and output rates
via direct digital synthesis
High accuracy digital architecture for stable PLL
dynamics combined with an APLL for low jitter final
output clocks
Selectable Automatic DPLL bandwidth control (auto*
selects either Locked bandwidth, or Acquisition
bandwidth), or Locked DPLL bandwidth (Reg. 3B
Bit 7)
Two programmable bandwidth controls:
Programmable damping factor, (For optional faster
locking and peaking control) Factors = 1.2, 2.5, 5,
10* or 20 (Reg. 6B, Bits [2:0])
Programmable DPLL pull-in frequency range (Reg. 41,
Reg. 42).
Phase loss fine limit. on*/off (Reg. 73 Bit 7) and
programmable range 0 to 7 Dec. (Reg. 73 Bits [2:0])
Multi-cycle phase loss course limit, on*/off (Reg. 74
Bit 7) and selectable range from ±(1 to 8191) UI in 13
steps (Reg. 74 Bits [3:0]).
Multi-cycle phase detector - Course phase detector &
capture range on*/off (Reg. 74 Bit 6) and selectable
range from ±(1 to 8191) UI in 13 steps (Reg. 74 Bits
[3:0]). If selected, this feature increases jitter and
wander tolerance to a maximum of 8192 UI (normally
limited to ±0.5 UI)
Use of coarse phase detector result in DPLL algorithm,
on*/off (Reg. 74 Bit 5) - speeds up phase locking
Limit DPLL1 Integral when at DPLL frequency limit,
on*/off (Reg. 3B Bit 3) - reduces overshoot
Anti-noise filter for low frequency inputs, on/off*
(Reg. 76 Bit 7).
DPLL1 PD2 gain enable, on*/off (Reg. 6D
Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
Reg. 6D Bits [2:0]). If off, PD2 is not used.
• Locked bandwidth: 18, 35* or 70 Hz (Reg. 67)
• Acquisition bandwidth: 18, 35 or 70* Hz
(Reg. 69)
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