ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 8

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Lock8K Mode
Lock8K mode automatically sets the divider parameters
to divide the input frequency down to 8 kHz. Lock8K can
only be used on the supported spot frequencies. See
divn_SEC1 and 2 descriptions (Bit 7 of Reg. 22 and 23,
cnfg_ref_source_frequency). Lock8k mode is enabled by
setting the Lock8k bit (Bit 6) in the appropriate
cnfg_ref_source_frequency register. Using lower
frequencies for phase comparisons in the DPLL results in
a greater tolerance to input jitter. It is possible to choose
which edge of the input reference clock to lock to, by
setting 8K Edge Polarity, (Bit 2 of Reg. 03, test_register1).
DivN Mode
In DivN mode, the divider parameters are set manually by
configuration (Bit 7 of the cnfg_ref_source_frequency
register), but must be set so that the frequency after
division is exactly 8 kHz.
The DivN function is defined as:
DivN = “Divide by N+ 1”, i.e. it is the dividing factor used
for the division of the input frequency, and has a value of
(N+1) where N is an integer from 1 to 12499 inclusive.
Therefore, in DivN mode the input frequency can be
divided by any integer value between 2 to 12499.
Consequently, any input frequency which is a multiple of
8 kHz, between 8 kHz to 125 MHz, can be supported by
using DivN mode.
Note...Both reference inputs can be set to use DivN
independently of the frequency and configuration of the other
input. However only one value of N is allowed, so if both inputs
have DivN selected, they must be running at the same
frequency.
DivN Examples
(a) To lock to 2.000 MHz:
(b) To lock to 10.000 MHz:
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
(i)
(ii) To achieve 8 kHz, the 2 MHz input must be
(i)
Set the cnfg_ref_source_frequency register to
10XX0000 (binary) to enable DivN, and set the
frequency to 8 kHz - the frequency required after
division. (XX = “Leaky Bucket” ID for this input).
divided by 250. So, if DivN = 250 = (N + 1)
then N must be set to 249. This is done by writing
F9 hex (249 decimal) to the DivN register pair
Reg. 46/47.
The cnfg_ref_source_frequency register is set to
10XX0000 (binary) to set the DivN and the
FINAL
Page 8
Selection of Input SECs
Initialization
Switching between inputs SEC1 and SEC2 is triggered
directly from a dedicated pin (SRCSW), though for the
device to operate properly, the device must first be
initialized by holding the pin High during reset and for at
least a further 251 ms after PORB has gone High (250 ms
allowance for the internal reset to be removed plus 1 ms
allowance for APLLs to start-up and become stable). A
simple external circuit to set SCRSW high for the required
period is shown in the “Simplified Application Schematic”
on page 70. If SCRSW is held Low at any time during the
251 ms initialization period, this will result in incorrect
device operation.
SEC Selection - SRCSW pin
After the ACS8526 has been initialized (see previous
“Initialization” section), then the value of SRCSW pin
directly selects either SEC1 (SRCSW High) or SEC2
(SRCSW Low). The default frequency tolerance of SEC1
and SEC2 is ±80 ppm (Reg. 41 and Reg. 42) with respect
to the local (calibrated) oscillator clock. These registers
can be subsequently set by external software, if required.
After initialization, the output clocks are stable and the
device will operate as a simple switch, with the DPLL
trying to lock on to the selected reference source.
Output Clock Phase Continuity on Source
Switchover
A phase offset between SEC inputs will be seen as a
phase shift on the output on source switchover equal to
the input phase offset.
Note...The ACS8526 has no Phase Build-out function to
accommodate this. If this function is required, it is available on
the AS8525 LC/P device.
The rate of change of phase on the output, during the time
between input switchover and the output settling to a
steady state, is dependent on factors of: input frequency,
(ii) To achieve 8 kHz, the 10 MHz input must be
frequency to 8 kHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 decimal) to the DivN
register pair Reg. 46/47.
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