ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 47

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Address (hex):
Address (hex):
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
MFrSync_en
Bit No.
Bit No.
Bit 7
[7:4]
[3:0]
Bit 7
7
62
63
cnfg_output_frequency
(Output O1)
Description
output_freq_O1
Configuration of the output frequency available at
Output O1. Many of the frequencies available are
dependent on the frequencies of the APLL1 and the
APLL2. These are configured in Reg. 64 and
Reg. 65. See “Output Frequency Selection by
Register Programming” on page 17.
Note...The values on the pins O1_FREQ [2:0] and
SONSDHB determine the default output frequency
for Output O1, which, at power-up/reset is written to
the cnfg_output_frequency register. The value in
this register can, after the initialization period
(251 ms after PORB goes High), be changed by
writing to it via the serial interface, however any
subsequent reset will cause this register’s value to
be overwritten by whatever value is on the pins at
the time of the reset. See “Output Frequency
Selection by Hardware” and Table 6 on page 18.
Not used.
cnfg_output_frequency
(MFrSync/FrSync)
FrSync_en
Description
MFrSync_en
Register bit to enable the 2 kHz Sync output
(MFrSync).
Bit 6
Bit 6
output_freq_O1
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 47
(R/W) Register to configure and
enable the frequencies available
on Output O1.
(R/W) Register to configure and
enable the frequencies available
on outputs MFrSync and FrSync.
Bit Value
Bit Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit 3
Bit 3
0
1
-
Value Description
Output disabled.
2 kHz.
8 kHz.
APLL1 frequency/2.
Digital1 (Reg. 39 cnfg_digital_frequencies).
APLL1 frequency.
APLL1 frequency/16.
APLL1 frequency/12.
APLL1 frequency/8.
APLL1 frequency/6.
APLL1 frequency/4.
APLL2 frequency/64.
APLL2 frequency/48.
APLL2 frequency/16.
APLL2 frequency/8.
APLL2 frequency/4.
-
Value Description
Output MFrSync disabled.
Output MFrSync enabled.
Bit 2
Bit 2
ACS8526 LC/P LITE
Default Value
Where XXXX is set by values on
Pins O2_FREQ[2:0] and
SONSDHB, See Note in [3:0]
description.
Default Value
Bit 1
Bit 1
DATASHEET
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0000 XXXX
1100 0000
Bit 0
Bit 0