ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 15

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE
G.813
0.2 dB. GR-253
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8526 provides a choice of damping
factors, with more choice given as the bandwidth setting
increases into the frequency regions classified as jitter.
Table 5 shows which damping factors are available for
selection at the different bandwidth settings, and the
corresponding jitter transfer approximate gain peak.
Table 5 Available Damping Factors for different DPLL
Bandwidths, and Associated Gain Peak Values
Phase/Frequency/Lock Detection
Two main types of detector are available in the ACS8526:
Phase and Frequency Detectors
There are two multi-phase and frequency detectors, one
for each DPLL. The multi-phase and frequency detectors
are used to compare input and feedback clocks. They
operate at input frequencies up to 77.76 MHz
(155.52 MHz is internally divided down to 77.76 MHz).
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
18
35
70
Bandwidth/Hz
Phase and frequency detectors, and
Phase Loss/Lock detectors.
[8]
) specify a wander transfer gain of less than
1
2
3, 4, 5
1
2
3
4, 5
1
2
3
4
5
[11]
Reg. 6B [2:0]
specifies jitter (not wander) transfer of
1.2
2.5
5
1.2
2.5
5
10
1.2
2.5
5
10
20
Factor selected
Damping
[13]
, G.812
0.4
0.2
0.1
0.4
0.2
0.1
0.06
0.4
0.2
0.1
0.06
0.03
Gain Peak/dB
[7]
and
FINAL
Page 15
A common arrangement however is to use Lock8k mode
(See Bit 6 of Reg. 22 and 23), where all input frequencies
are divided down to 8 kHz internally. Marginally better
MTIE figures may be possible in direct lock mode due to
more regular phase updates. This direct locking capability
is one of the unique features of the ACS8526.
A multi-phase detector (patent pending) approach is used
in order to give an infinitesimally small input phase
resolution combined with large jitter tolerance. A
multi-phase detector comprises the following phase
detectors:
The phase detectors can be configured to be immune to
occasional missing input clock pulses by using nearest
edge detection (±180°capture) or the normal ±360°
phase capture range which gives frequency locking. The
device will automatically switch to nearest edge locking
when the multi-UI phase detector is not enabled, and the
other phase detectors have detected that phase lock has
been achieved. It is possible to disable the selection of
nearest edge locking via Reg. 03 Bit 6 (set to 1). In this
setting, frequency locking will always be enabled.
The balance between the first two types of phase detector
employed can be adjusted via Reg. 6A to 6D. The default
settings should be sufficient for all modes. Adjustment of
these settings affects only small signal overshoot and
bandwidth.
The multi-cycle phase detector (wide-range) is enabled via
Reg. 74, Bit 6 set to 1 and the range is set in exponentially
increasing steps from ±1 UI up to 8191 UI via Reg. 74,
Bits [3:0].
When this detector is enabled it keeps a track of the
correct phase position over many cycles of phase
difference to give excellent jitter tolerance. This provides
an alternative to switching to Lock8k mode as a method
of achieving high jitter tolerance.
An additional control (Reg. 74 Bit 5) enables the
multi-phase detector value to be used in the final phase
value as part of the DPLL loop. When enabled by setting
High, the multi cycle phase value will be used in the loop
and gives faster pull-in (but more overshoot).
Phase and frequency detector (±360°, or ±180°
range).
An Early/Late phase detector for fine resolution.
A multi-cycle phase detector for large input jitter
tolerance (up to 8191 UI), which captures and
remembers phase differences of many cycles
between input and feedback clocks.
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