ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 25

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

“Digital” Frequencies
Table 13, “O1 and O2 Output Frequency Selection,” lists
Digital1 and Digital2 as available for selection. Digital1 is
a single frequency selected from the range shown in
Table 13 O1 and O2 Output Frequency Selection
Using Output O2 to Control Pulse Width of 2/8 kHz on FrSync,
MFrSync and 01 Outputs
It can be seen from Table 13 (01 and 02 Output
Frequency Selection) that frequencies listed as 2 kHz and
8 kHz can be selected. Whilst the FrSync and MFrSync
outputs are always supplied from DPLL1, the 2 kHz and
8 kHz options available from the O1 and O2 outputs are
all supplied via DPLL1 or DPLL2 (Reg. 7A Bit 7).
The outputs can be either clocks (50:50 mark-space) or
pulses, and can be inverted. When pulse configuration is
used, the pulse width will be one cycle of the rate selected
on Output O2 (Output O2 must be configured to generate
at least 1,544 kHz to ensure that pulses are generated
correctly). Figure 6 shows the various options with the
8 kHz controls in Reg. 7A. There is an identical
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Value in Register
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Output Frequency for given “Value in Register” for each Output Port’s Cnf_output_frequency Register
Reg. 61 Bits [3:0]
Output O2
APLL1/48
APLL1/16
APLL1/12
APLL2/64
APLL2/48
APLL2/16
APLL1/8
APLL1/6
APLL1/4
APLL2/8
APLL2/4
Digital2
Digital1
2 kHz
8 kHz
Off
FINAL
Page 25
Table 14. Digital2 is another single frequency selected
from the same range.
arrangement with Reg. 7A Bits [1:0] for the 2 kHz 01 and
MFrSync outputs. Outputs FrSync and MFrSync can be
disabled via Reg. 63 Bits [7:6].
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced
Low. The reset is asynchronous, the minimum Low pulse
width is 5 ns. Reset is needed to initialize all of the
register values to their defaults. Reset must be asserted
at power on, and may be re-asserted at any time to restore
defaults. This is implemented simply using an external
capacitor to GND along with the internal pull-up resistor.
The ACS8526 is held in a reset state for 250 ms after the
PORB pin has been pulled High. In normal operation PORB
should be held High.
ACS8526 LC/P LITE
Reg. 62 Bits [7:4]
Output O1
APLL1/16
APLL1/12
APLL2/64
APLL2/48
APLL2/16
APLL1/2
APLL1/1
APLL1/8
APLL1/6
APLL1/4
APLL2/8
APLL2/4
Digital1
2 kHz
8 kHz
Off
DATASHEET
www.semtech.com