FAN6300DY Fairchild Semiconductor, FAN6300DY Datasheet - Page 11

• Manufacturer Part Number: FAN6300DY
• Description: Fan6300 - Highly Integrated Quasi-resonant Current Mode Pwm Controller
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
Current Sensing and PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current sense signal and V
pin reaches around V
is terminated immediately. V
a variable voltage around 0.8V for output power limit.
Leading Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking
time is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply V
from the auxiliary winding of the main transformer. V
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply V
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Over-Power Compensation
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of R
also affects the H/L line constant power limit.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
LIMIT
DD
until energy can be delivered
= (V
FB
LIMIT
. When the voltage on CS
FB
-1.2)/3, the switch cycle
is internally clamped to
DD
during startup.
DET
is higher. R
DET
DD
V
V
abnormal conditions. Once the V
V
for t
switching operation.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs blanking time ignores the leakage
inductance ringing. A voltage comparator and a 2.5V
reference voltage develop an output OVP protection.
The ratio of the divider determines the sampling voltage
of the stop gate, as an optical coupler and secondary
shunt regulator are used. If the DET pin OVP is
triggered, power system enters latch-mode until AC
power is removed.
Short-Circuit and Open-Loop Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
t
turned-off, the supply voltage V
When V
V
down. V
of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 23. Voltage Sampled After 4μs Blanking Time
D-OLP
DD
DD
DD
DD
11
VDDOVP
decreases to 8V, then the controller is totally shut
over-voltage protection voltage (V
Over-Voltage Protection
over-voltage protection prevents damage due to
, PWM output is turned off. As PWM output is
DD
DD
, controller enters latch mode and stops all
is charged up to the turn-on threshold voltage
goes below the PWM-off threshold of 10V,
After Switch-off Sequence
DD
begins decreasing.
DD
voltage is over the
DD-OVP
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) and lasts