IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 10

• Manufacturer Part Number: IDT72V265LA15TFI
• Description: IC FIFO SS 16384X18 15NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA15TFI

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA15TFI

SERIAL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a combi-
nation of the LD, SEN, WCLK and SI input pins. Programming PAE and
PAF proceeds as follows: when LD and SEN are set LOW, data on the SI
input are written, one bit for each WCLK rising edge, starting with the Empty
Offset LSB and ending with the Full Offset MSB. A total of 26 bits for the
IDT72V255LA and 28 bits for the IDT72V265LA. See Figure 13, Serial
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
lectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written
to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in sequence is writ-
ten to the registers via SI. If an interruption of serial programming is de-
sired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN
LOW and deactivate LD. Once LD and SEN are both restored to a LOW
level, serial offset programming continues.
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus t
will be valid after the next two rising RCLK edges plus t
PARALLEL MODE
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. ProgrammingPAE
and PAF proceeds as follows: when LD and WEN are set LOW, data on
the inputs Dn are written into the Empty Offset Register on the first LOW-to-
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK,
data are written into the Full Offset Register. The third transition of WCLK
writes, once again, to the Empty Offset Register. See Figure 14, Parallel
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers.
A Master Reset initializes both pointers to the Empty Offset (LSB) register.
A Partial Reset has no effect on the position of these pointers.
programming sequence. In this case, the programming of all offset
registers does not have to occur at one time. One, two or more offset
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
If Serial Programming mode has been selected, as described above, then
Using the serial method, individual registers cannot be programmed se-
Write operations to the FIFO are allowed before and during the serial
From the time serial programming has begun, neither partial flag will be
It is not possible to read the flag offset values in a serial mode.
If Parallel Programming mode has been selected, as described above,
The act of writing offsets in parallel employs a dedicated write offset
Write operations to the FIFO are allowed before and during the parallel
PAE
plus t
SKEW2
PAF
, PAE
.
10
registers can be written and then by bringing LD HIGH, write operations
can be redirected to the FIFO memory. When LD is set LOW again, and
WEN is LOW, the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel programming can
also be interrupted by setting LD LOW and toggling WEN.
the programming process. From the time parallel programming has
begun, a partial flag output will not be valid until the appropriate offset word
has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid
after two more rising WCLK edges plus t
next two rising RCLK edges plus t
register pointer. The contents of the offset registers can be read on the
Q
Qn from the Empty Offset Register on the first LOW-to-HIGH transition of
RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are read
from the Full Offset Register. The third transition of RCLK reads, once
again, from the Empty Offset Register. See Figure 15, Parallel Read of
Programmable Flag Registers, for the timing diagram for this mode.
or writes to the FIFO. The interruption is accomplished by deasserting
REN, LD, or both together. When REN and LD are restored to a LOW level,
reading of the offset registers continues where it left off. It should be noted,
and care should be taken from the fact that when a parallel read of the flag
offsets is performed, the data word that was present on the output lines Qn
will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the
beginning of memory.
edge. REN and WEN must be HIGH before bringing RT LOW. At least one
word, but no more than D –2 words should have been written into the
FIFO between Reset (Master or Partial) and the time of Retransmit setup.
D = 8,192 for the IDT72V255LA and D = 16,384 for the IDT72V265LA.
In FWFT mode, D = 8,193 for the IDT72V255LA and D = 16,385 for the
IDT72V265LA.
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
Retransmit setup requires a LOW on REN to enable the rising edge of RCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
0
Note that the status of a partial flag (PAE or PAF) output is invalid during
The act of reading the offset registers employs a dedicated read offset
It is permissible to interrupt the offset register read sequence with reads
The Retransmit operation allows data that has already been read to be
Retransmit setup is initiated by holding RT LOW during a rising RCLK
If IDT Standard mode is selected, the FIFO will mark the beginning of
When EF goes HIGH, Retransmit setup is complete and read operations
-Qn pins when LD is set LOW and REN is set LOW. Data are read via
Parallel reading of the offset registers is always permitted regardless of
PAE
COMMERCIAL AND INDUSTRIAL
plus t
PAF
SKEW2
TEMPERATURE RANGES
, PAE will be valid after the
.
OCTOBER 22, 2008