IDT72V265LA15TFI IDT, Integrated Device Technology Inc, IDT72V265LA15TFI Datasheet - Page 12

• Manufacturer Part Number: IDT72V265LA15TFI
• Description: IC FIFO SS 16384X18 15NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V265LA15TFI

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V265LA15TFI

SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D17)
CONTROLS:
MASTER RESET (MRS)
LOW state. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF
will go HIGH.
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
describing the LD pin for further details.)
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
PARTIAL RESET (PRS)
LOW state. As in the case of the Master Reset, the internal read and write
pointers are set to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
or First Word Fall Through, that mode will remain selected. If the IDT
Standard mode is active, then FF will go HIGH and EF will go LOW. If the
First Word Fall Through mode is active, then OR will go HIGH, and IR will
go LOW.
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
operation, when reprogramming partial flag offset settings may not be
convenient.
RETRANSMIT (RT)
accessed again. There are two stages: first, a setup procedure that resets
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
Data inputs for 18-bit wide data.
A Master Reset is accomplished whenever the MRS input is taken to a
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
Parallel reading of the registers is always permitted. (See section
During a Master Reset, the output register is initialized to all zeroes. A
See Figure 5, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to a
Whichever mode is active at the time of Partial Reset, IDT Standard mode
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
The Retransmit operation allows data that has already been read to be
If LD is HIGH during Master Reset, then PAE is assigned a threshold
If FWFT is LOW during Master Reset then the IDT Standard mode,
12
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at beginning of
the memory.
edge. REN and WEN must be HIGH before bringing RT LOW.
Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following Re-
transmit setup requires a LOW on REN to enable the rising edge of RCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
transmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is neces-
sary. Reading all subsequent words requires a LOW on REN to enable the
rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for
the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
SI input determines whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO memory. It also uses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
WRITE CLOCK (WCLK)
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
If IDT Standard mode is selected, the FIFO will mark the beginning of the
When EF goes HIGH, Retransmit setup is complete and read operations
If FWFT mode is selected, the FIFO will mark the beginning of the Re-
When OR goes LOW, Retransmit setup is complete; at the same time, the
This is a dual purpose pin. During Master Reset, the state of the FWFT/
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
A write cycle is initiated on the rising edge of the WCLK input. Data setup
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008